Latest threads in Field-Programmable Gate Arrays

Differential to single ended convertion in FPGA

Hi, I want to convert a differential digital signal to single ended signal. But, because of skew, the positive and nega...

0 19yrs

prathap.ap

0 19yrs prathap.ap

Spartan3E price update ?

It's about a year that Spartan3E are on the market but i am still confused on pricing. On: http://www.xilinx.com/produc...

3 19yrs

tullio.grassi

3 19yrs tullio.grassi

Need examples/instruction: use of altpll_reconfig (Altera)

For some reason, I'm not getting how to create the various .mif files to initialize enhanced PLLs with Quartus II. I'm...

3 19yrs

rjmyers

3 19yrs rjmyers

Simple questions on IDELAYCTRL

I can't seem to find a document that calls out the XY locations for the IDELAYCTRL. Where is this information found? Wh...

18 19yrs

lecroy7200

18 19yrs lecroy7200

Input setup time & Hold Input

Hi!, I am developing a complex system and at this moment I would like to test one of its blocks: block_B. This block re...

1 19yrs

jmunir

1 19yrs jmunir

Q on duty cycle

Hi, I am new to VHDL and working on a clock divider but I don't get 50% duty cycle for all divisors. Can anyone explain...

1 19yrs

bhavanireddy

1 19yrs bhavanireddy

false path

Hi . Can anyone throw some light on false path and how to determine it during synthesis.

1 19yrs

jesuraj.vinoth

1 19yrs jesuraj.vinoth

query in delay chains

I am using cyclone/cyclone II FPGA.I am using 120 delay chains with help of # command in verilog.Problem is 10 channel...

0 19yrs

vsrpkumar

0 19yrs vsrpkumar

Spartan-3E slice resources

Hi all, I'm a bit confuse about the Spartan-3E datasheet. How many SRL16 and FDE inside single slice (SLICEM) anyway ?...

4 19yrs

kunilkuda

4 19yrs kunilkuda

Virtex-4 DDR RAM Usage (with VHDL)

Hello, I'm trying to access the DDR SDRAM of a Virtex-4 ML403 Evaluation board (XC4VFX12-10). I downloaded the referenc...

0 19yrs

newsgroups

0 19yrs newsgroups

spartan-3e starter kit and ethernet

Hello, I recently purchased a spartan-3e starter kit from Xilinx. (I have so far been unimpressed with the reference de...

0 19yrs

hakan.aydin

0 19yrs hakan.aydin

Re: board - T562.jpg

>John Lark>> >> >>> John Lark>>>> This is the thing I'm working on this month. It's a delay generator, >>>> with an MC6...

97 19yrs

jjlarkin

97 19yrs jjlarkin

EDK 8.2 Block RAM error

hi, it seems that either EDK 8.2 or ISE 8.2 has still some issues with the BRAM inits, if an EDK system has more than 1...

15 19yrs

Antti.Lukats

15 19yrs Antti.Lukats

master support for OPB device

Hi, There seems to be an error in the MASTER_CNTL_STATE_MACHINE in the /pcores//hdl/vhdl/user_logic.vhd "user logic mas...

1 19yrs

get2venu

1 19yrs get2venu

IDELAY setup/hold

According to the Virtex 4 data sheet, the setup/hold window widens considerably when using non-zero IDELAY delay (eithe...

0 19yrs

tom.derham

0 19yrs tom.derham

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