Field-Programmable Gate Arrays

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Spartan3E price update ?

It's about a year that Spartan3E are on the market but i am still confused on pricing. On: http://www.xilinx.com/produc...
3 comments posted 19yrs
posted by tullio.grassi
3 comments posted 19yrs posted by tullio.grassi

Simple questions on IDELAYCTRL

I can't seem to find a document that calls out the XY locations for the IDELAYCTRL. Where is this information found? Wh...
18 comments posted 19yrs
posted by lecroy7200
18 comments posted 19yrs posted by lecroy7200

Input setup time & Hold Input

Hi!, I am developing a complex system and at this moment I would like to test one of its blocks: block_B. This block re...
1 comments posted 19yrs
posted by jmunir
1 comments posted 19yrs posted by jmunir

Q on duty cycle

Hi, I am new to VHDL and working on a clock divider but I don't get 50% duty cycle for all divisors. Can anyone explain...
1 comments posted 19yrs
posted by bhavanireddy
1 comments posted 19yrs posted by bhavanireddy

false path

Hi . Can anyone throw some light on false path and how to determine it during synthesis.
1 comments posted 19yrs
posted by jesuraj.vinoth
1 comments posted 19yrs posted by jesuraj.vinoth

query in delay chains

I am using cyclone/cyclone II FPGA.I am using 120 delay chains with help of # command in verilog.Problem is 10 channel...
0 comments posted 19yrs
posted by vsrpkumar
0 comments posted 19yrs posted by vsrpkumar

Spartan-3E slice resources

Hi all, I'm a bit confuse about the Spartan-3E datasheet. How many SRL16 and FDE inside single slice (SLICEM) anyway ?...
4 comments posted 19yrs
posted by kunilkuda
4 comments posted 19yrs posted by kunilkuda

Virtex-4 DDR RAM Usage (with VHDL)

Hello, I'm trying to access the DDR SDRAM of a Virtex-4 ML403 Evaluation board (XC4VFX12-10). I downloaded the referenc...
0 comments posted 19yrs
posted by newsgroups
0 comments posted 19yrs posted by newsgroups

spartan-3e starter kit and ethernet

Hello, I recently purchased a spartan-3e starter kit from Xilinx. (I have so far been unimpressed with the reference de...
0 comments posted 19yrs
posted by hakan.aydin
0 comments posted 19yrs posted by hakan.aydin

Re: board - T562.jpg

>John Lark>> >> >>> John Lark>>>> This is the thing I'm working on this month. It's a delay generator, >>>> with an MC6...
97 comments posted 19yrs
posted by jjlarkin
97 comments posted 19yrs posted by jjlarkin

EDK 8.2 Block RAM error

hi, it seems that either EDK 8.2 or ISE 8.2 has still some issues with the BRAM inits, if an EDK system has more than 1...
15 comments posted 19yrs
posted by Antti.Lukats
15 comments posted 19yrs posted by Antti.Lukats

master support for OPB device

Hi, There seems to be an error in the MASTER_CNTL_STATE_MACHINE in the /pcores//hdl/vhdl/user_logic.vhd "user logic mas...
1 comments posted 19yrs
posted by get2venu
1 comments posted 19yrs posted by get2venu

IDELAY setup/hold

According to the Virtex 4 data sheet, the setup/hold window widens considerably when using non-zero IDELAY delay (eithe...
0 comments posted 19yrs
posted by tom.derham
0 comments posted 19yrs posted by tom.derham

Static Timing Analysis vs Dinamic Timing Analysis

Hi!, Could anybody explain me these concepts and their differences?. And what is done in foundation ISE tool of xilinx?....
1 comments posted 19yrs
posted by jmunir
1 comments posted 19yrs posted by jmunir