Hi,
I am new to VHDL and working on a clock divider but I don't get 50% duty cycle for all divisors. Can anyone explain me the effect of irregular or non 50% duty cycle clock to digital logic circuits?
Thanks in advance BR
If you use the rising edge of the clock exclusively (as is generally the case with most synchronous designs) then duty cycle of the clock is irrelevant as long as the 'high time' and 'low time' also meet the specs for the part that you're using.
If you use both rising and falling edges of the clock then duty cycle is very important since it directly impacts the time between the rising and falling edges.
KJ
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