I am using cyclone/cyclone II FPGA.I am using 120 delay chains with help of # command in verilog.Problem is 10 channel constitute one channel .12 channels are there.Some delay chains are differing with remaining in delays.How to constraint in FPGA with quartus 6.0 s/w so that all delays will be same for all 12 channels.I am using for DSP applications kumar
- posted
17 years ago