For some reason, I'm not getting how to create the various .mif files to initialize enhanced PLLs with Quartus II. I'm trying to target a Stratix II device. The situation that I'm in will require me to reconfigure the PLL's divisors dependent upon the state of an input pin on the FPGA.
Anyone got a step-by-step set of instructions that cleary describe how to do this?
Hi Bob, Please see if the user guide available at
H> For some reason, I'm not getting how to create the various
Hi Bob, also check out
which will have more Stratix II specific > Hi Bob,
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Hi;
I went back to look at this topic again (had other fires to fight first).
For the life of me, I can't find the divide-by-6 or divide-by-12 value in the .MIF file that Quartus generates (hopefully I recompiled the project correctly -- no instructions in the downloaded example files for example #1).
I've put a ticket into Altera's "mySupport" helpdesk, asking for more detailed info on how to do this. (My local supplier's FAE hasn't run into using ALTPLL and ALTPLL_RECONFIG cases yet).
-Bob
Subroto Datta wrote:
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