Input setup time & Hold Input

Hi!,

I am developing a complex system and at this moment I would like to test one of its blocks: block_B. This block receives its input signals from a different block_A and a third one: block_C controls the hold_inputs of each flip-flop contained in the block_B.

When I prepare the test_bench with the "test bench waveform tool", my doubt comes when I have to model the behaviour of the hold_input which feeds the block_B. The test bench waveform asks me for inserting the "input setup time" and I notice that the Xilinx tool consider the "hold_input" an input from one IOB which is not true. If I insert a 0 (zero) into the "input setup time" box I have an error in the simulation since there is an "high VIOLATION ON CE WITH RESPECT TO CLK", so I understand that I have to increase the value of that time but, How much?

My question is: How do I have to model the inputs coming from other blocks of the system (not from IOBs), like "hold_input" from block_C or "input signals" from block_A?.

Thanx

Jajo.

Reply to
jajo
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Hopefully you are not trying to do a timing simulation until you have completed a logic simulation. Timing is typically analyzed with a static timing analysis on the routed design. But there is little point in doing this before you have a completed chip design other than as a cursory check. This is because the timing will change each time you Place & Route. As more of the chip is used the timing typically gets worse. So initially each module should meet it timing constraints easly. This may not show in a timing analysis because the tool routes to meet timing, not to exceed it.

The first thing you need to do is a logic simulation where you don't worry about the timing at all. This makes it easier to focus on getting the logic correct. Once the logic is right you can worry about timing.

When you simulate a design for an FPGA, it typically assumes your external inputs are I/Os. I have never used the test bench toll you are describing, I have always written my own test bench code. Just give the tool what it needs to work without error. How much actual setup and hold time you need in your real design depends on how you are designing your module interfaces. Typically you might put FFs at each of the module outputs, or possibly the inputs, but this is a design decision and you might not have FFs on either of the modulel IOs depending on what you are doing. Where you do have FFs, you would use the data sheet setup and hold times for the FF.

Reply to
rickman

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