Hi!,
I am developing a complex system and at this moment I would like to test one of its blocks: block_B. This block receives its input signals from a different block_A and a third one: block_C controls the hold_inputs of each flip-flop contained in the block_B.
When I prepare the test_bench with the "test bench waveform tool", my doubt comes when I have to model the behaviour of the hold_input which feeds the block_B. The test bench waveform asks me for inserting the "input setup time" and I notice that the Xilinx tool consider the "hold_input" an input from one IOB which is not true. If I insert a 0 (zero) into the "input setup time" box I have an error in the simulation since there is an "high VIOLATION ON CE WITH RESPECT TO CLK", so I understand that I have to increase the value of that time but, How much?
My question is: How do I have to model the inputs coming from other blocks of the system (not from IOBs), like "hold_input" from block_C or "input signals" from block_A?.
Thanx
Jajo.