Latest threads in Field-Programmable Gate Arrays

Question concerning XAPP224

hi newsgroup, in the Xilinx application note "XAPP224.pdf" it is said (chapter: Using the Received Data) : "Some exampl...

1 19yrs

ALuPin

1 19yrs ALuPin

Free Anydivider, Divide clock by any number

Hi, I have just finished this free commercial grade tool. I wish it is useful. Topweaver Anydivider (TAD) is a GUI base...

13 19yrs

topweaver

13 19yrs topweaver

Using quartus "In system memory editor" from command line

Hi folks, Does anyone know wether it is possible to use the quartus "In system memory editor" feature from command line...

1 19yrs

sderrienREMOVE

1 19yrs sderrienREMOVE

Readback Jtag Problem

When I make the readback on the Spartan II concerning a configuration's bitstream which changes the state of some flip...

2 19yrs

happy_pippo81

2 19yrs happy_pippo81

Spartan3 IBIS / Simulation questions

Hi, I have a design with a Spartan3E driving some PCI logic. I'm trying to simulate part of the design using HyperLynx...

0 19yrs

xjjzdv402

0 19yrs xjjzdv402

Xilinx EDK/XPS 8.2 freezes XP desktop when launching XMD

Hi everyone, When I launch an external application such as XMD, the Software Debugger or Platform Studio SDK from the X...

0 19yrs

mpthompson

0 19yrs mpthompson

Can you configure an Altera Stratix without the nStatus line?

Hello all, I recently bought one of the Parallax Stratix "SmartPack" boards on eBay. It was a good deal, and the FPGA w...

3 19yrs

jshamlet

3 19yrs jshamlet

XEM3010

Hi, A part of my project needs the FPGA spartan3 ( XC3S100) to be interfaced with the USB via FIFO. I made the FIFO usi...

2 19yrs

conphiloso

2 19yrs conphiloso

coherent logic

Has anyone heard of digital design technique, method or theory called "coherent logic" design?

0 19yrs

jshanton

0 19yrs jshanton

how can I use DCM in paritial reconfiguration design?

I have a Virtex-II oro Partial Reconfiguration design which contain several modules such as PPC,PLB.OPB,DCM,DDR and so...

0 19yrs

wangw8021

0 19yrs wangw8021

EDk and DCM

HI I'm working on an microblaze project and i'm stuck at a problem with a dcm. i generated a new project with the wizar...

9 19yrs

u_stadler

9 19yrs u_stadler

Picoblaze C compiler 1.8.4

Hi all, for the picoblaze funs... you can download the latest version of picoblaze C compiler on my website www.poderic...

3 19yrs

francesco_poderico

3 19yrs francesco_poderico

Buggy behaviour in Modelsim, when reading from pipe?

Hi All, I had to integrate a VHDL testbench of complex system with the Python software (which is used to control the re...

2 19yrs

wzab

2 19yrs wzab

LUT input order

Hey ppl Is there a way we can have a control over the input order of the LUTs...I see that eventhough we specify the in...

10 19yrs

bharadwaj.sr

10 19yrs bharadwaj.sr

Digitally Controlled Impedance with Lattice ECP2M FPGA's

Does anyone know if the LATTICE ECP2M FPGA's have on die Digitally Controlled Impedance (DCI) matching for input LVDS?...

2 19yrs

slkjas

2 19yrs slkjas

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