Hi,
I have a design with a Spartan3E driving some PCI logic. I'm trying to simulate part of the design using HyperLynx 7.5 and the Spartan3e IBIS model from Xilinx.
- When I set the I/O standard for the pin(s) in question, the steady-state output high voltage is 3V, not 3.3V . I know Xilinx only claims PCI 3.3V compatability if the I/Os are run at 3V -- is this output voltage hard coded in the IBIS model?
I think all the power supplies in HyperLynx are correctly set, including the 3.3V supply.
- In HyperLynx, when I change the I/O standard for the pin (i.e. LVCMOS, SSTL, etc) the "pin number" for the selected pin seems to change. Is this "pin number" just refering to an I/O standard the IBIS file supports?
- Xilinx XAP653 has some guidelines for PCI and clamp diode / resistor calculations. Page 2 seems to be a bit circular when it comes to computing the resistance to limit the current, and more specifically the foward voltage for the didoe . Where does the knowledge of using
Your help is welcome.
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