Free Anydivider, Divide clock by any number

Hi Peter Alfke, Thanks for viewing Topweaver Anydivider (TAD). In fact the feature you said has been realized by TAD. And it is only a part of TAD. If TAD can only generate the "n and n-1 consecutive pulses", I can not name it ANY. The waveform of the output clock can be either from automatical calculation or from visual adjustment. The example of 4/11 is in manual mode, to illustrate how to drag the waveform to anything you want. And the performance report shows a jitter of 22.40437%. "A good solution" can be generated in the auto mode, which is shown in the first picture. A strong point of TAD is the powerful analysis ability, which can help the engineers to choose the best waveform.

TAD

"Peter Alfke =D0=B4=B5=C0=A3=BA "

Very interesting program. I have a suggestion for code implementation to work better in Xilinx (and possibly other) FPGA's. Your code uses clock gating to generate narrow pulses. At least in Xilinx FPGA's it is not a good assumption that the Q output of a flip-flop has a longer delay to the gate input than the clock does. In fact, depending on the placement, a route from a global clock to a LUT input can be several nanoseconds. This can cause glitches even when you use the "correct" phase of the clock in your output logic. I would suggest using only flip-flop outputs to generate the module output, using XOR functions as necessary to generate outputs using both clock edges. The global clock routing to the flip-flop clocks is much better than you can do routing a global clock to a LUT input (or flip-flop D).

For waveforms that change on both input clock edges, It should be possible to generate the output as the XOR of just two flip-flops, one clocked on each edge. One of the flip-flops would toggle at each edge in the output waveform. At higher input clock rates this method also gives improved duty cycle accuracy, as the clock to output path on each edge looks like one flip-flop clock to Q delay followed by one LUT delay. Differences in clock-to-Q for rising vs falling edge flip-flops are small compared to routing delays in the FPGA.

Regars, Gabor

Let me explain what I mean with n and n-1.

If you want to reduce the number of pulses per unit time (that's what you are do> Hi Peter Alfke,

Sounds to me like the good old SN7497 "binary rate multiplier".

Yup. Rate multipliers also make good DACs, if you want DC from a RC integrator. Smaller to code than PWM, and higher frequency corner.

-jg

Hi Peter Alfke, I think we are describing the same thing. In the first picture

"Peter Alfke =D0=B4=B5=C0=A3=BA "

Hi Gabor, Thanks very much for your suggestion. Maybe I can fulfill it at this weekend. Before the new release, I will post the sample generated verilog code here. TAD

"Gabor =D0=B4=B5=C0=A3=BA "

Hi, Based on the suggestion of Gabor, I have revised Anydivider to generate the following sample code. Some other new features have also been added. The comparison between DLL/PLL and TAD will also be added in the document. Topweaver Anydivider 1.1 will be released soon after the final test.

TAD

/***********************************************************************************

Module Name : tad Fout/Fin : 4/11 Duty Cycle : 50.00000% Jitter : 0.82645% Website :

module tad ( input rst , input clk , output reg error , output clko ); reg [3:0] cnt ; reg h ; reg l ; always @(posedge clk)begin if(rst==1'b1)begin cnt

/***********************************************************************************

Hi, Topweaver Anydivider (TAD) 1.1 has been released. DLL/PLL resources provide a good way to frequency synthesis. But sometimes people write their own HDL code to fulfill the clock division function, for special multiply/divide values, adjustable duty cycle or other requirements that can hardly be achieved by using a DLL/PLL.

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TAD