how can I use DCM in paritial reconfiguration design?

I have a Virtex-II oro Partial Reconfiguration design which contain several modules such as PPC,PLB.OPB,DCM,DDR and so on. The EDK tool automaticly generate the modules and then I add tw accelerators which attach to the OPB through the IPIF.I generate th bitstream in the EDK,and it create the .ngc files,then I modify th top.vhd file and add the busmacros between the OPB bus and th accelerators.After that I systhesis the top.vhd file separately. And then I begin to implement the modular design.there is an error i the active implementation phase of the DCM module when I map the top.ng file(map top.ngd): ERROR:LIT:144 - Only STATUS0, STATUS1 and STATUS2 can be used in DCM symbol "dcm_0/dcm_0/DCM_INST" (output signal=dcm_0/dcm_0/CLK0_BUF). how can I solve this problem?