Field-Programmable Gate Arrays

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Manually creating a LUT in VHDL

Does anyone know if it is possible to define the values in a lookup table using VHDL compatible with Xilinx tools? If so...
4 comments posted 19yrs
posted by dpmontminy
4 comments posted 19yrs posted by dpmontminy

CCLK Virtex4 IBIS model.

Guys, In a recent thread here on VAF we learnt, more or less, that a large part of the Virtex-4's Cpin of 10pF is due t...
5 comments posted 19yrs
posted by symon_brewer
5 comments posted 19yrs posted by symon_brewer

MICROBLAZE AND OPB: TOO SLOW FOR VGA

Has anybody tried to write a code for crontroling what you put in a VGA port?? I have a Spartan 3E, and I want to put a...
8 comments posted 19yrs
posted by pbantunez
8 comments posted 19yrs posted by pbantunez

CPLD speed/temperature equivalent

I have a ALTERA MAX3000A CPLD with two inscriptions: EPM3256AFC256-7 --> commercial temp, speed grade 7 and EPM3256AFI2...
1 comments posted 19yrs
posted by manfred.balik
1 comments posted 19yrs posted by manfred.balik

Tracing UNKNOWN drivers

On Post Map and Post Route model simulations intermittently I get few X bytes. I set up a trace check for source in Mod...
2 comments posted 19yrs
posted by yaseenzaidi
2 comments posted 19yrs posted by yaseenzaidi

Spartan 3E Starter Kit Woes

I'm using ISE 8.2i and XPS 8.2i with a new Xilinx Starter Kit (the XC3S500efg320-4 FPGA on a Rev D board) and can not g...
10 comments posted 19yrs
posted by dave
10 comments posted 19yrs posted by dave

Board for sale

I couldn't find any rules for this group, so I am sorry if this is inappropriate. I just finished up a project I was wo...
0 comments posted 19yrs
posted by karrelsj
0 comments posted 19yrs posted by karrelsj

Need book for verilog on xc9536?

Required a book or web reference or examples suitable for xilinx xc9635 familiy. Thanks.
3 comments posted 19yrs
posted by <212>
3 comments posted 19yrs posted by <212>

Dynamic DCM Controller help

Hi, I'm interfacing 2 ADC to spartan 3 3s400. I need to phase shift th "DATA READY" from ADC with DCM and I'm not succe...
2 comments posted 19yrs
posted by ckh827
2 comments posted 19yrs posted by ckh827

ANN: PicoBlaze C: compile to bitstream!

PicoBlaze C compiler has been available for some time already, but until yesterday I never tried it. But today when I t...
10 comments posted 19yrs
posted by antti
10 comments posted 19yrs posted by antti

PowerPC_simulation

Does anybody know how can I simulate with Modelsim a design that containts a PowerPC in a Virtex-II Pro FPGA? I have do...
1 comments posted 19yrs
posted by
1 comments posted 19yrs posted by

interrupt handling using microblaze with XPS

Hi, I am pretty new to the arena of interrupt handling and would need some help. I am currently using microblaze v4.00a...
3 comments posted 19yrs
posted by chrisdekoh
3 comments posted 19yrs posted by chrisdekoh

PLL minimum input clock frequency

Hello all, I would like to multiply by 4 a USB chip 12MHz clock. The phase shift is not important. I cannot use Lattice...
4 comments posted 19yrs
posted by ndf123456789
4 comments posted 19yrs posted by ndf123456789