Field-Programmable Gate Arrays

Xilinx Quiz: 150/3 = ?

Quiz: what is DCM CLKFX output frequncy if the CLKFX Divisor is set to 3 in MHS file and input clock is 150MHz? snippet...

3 comments posted 19yrs

posted by Antti.Lukats

3 comments posted 19yrs posted by Antti.Lukats

words of the day

DOE: Female of paid knight. Bolting: We golf course. Reddish: Get a pilounce.

0 comments posted 19yrs

posted by fritz

0 comments posted 19yrs posted by fritz

Re: unexplainable Problem on Spartan 3

You might try a different approach. You say you have verified all the pieces separately. If so, you know the code segme...

2 comments posted 19yrs

posted by gnuarm

2 comments posted 19yrs posted by gnuarm

Integrating Atera “FFT MegaCore Function” in Mentor FPGA Advantage 7.2

Hi, I want to use the Atera ?FFT MegaCore Function? in a Design created with Mentor FPGA Advantage 7.2. Importing the c...

0 comments posted 19yrs

posted by friedrich_kiesel

0 comments posted 19yrs posted by friedrich_kiesel

C2H problems

Hi! i've tried to implement an very simple example to evaluate C2H. i've accelerated a function named testalg. c2h comp...

3 comments posted 19yrs

posted by hse02009

3 comments posted 19yrs posted by hse02009

Operate on RAM through FPGA

hi, I've formulate my problem in this page. Perhaps can someone tell me, what kind of typical error can made, when oper...

2 comments posted 19yrs

posted by zhongqiang.cheng

2 comments posted 19yrs posted by zhongqiang.cheng

jtag reset seq

I have a simple doubt about resetting sequence of Tap state machine One way of resetting TAP FSM is through trst signal...

9 comments posted 19yrs

posted by gautamsharma24

9 comments posted 19yrs posted by gautamsharma24

Frequency divider ?

I feel it is better to start a new thread, I have compiled my divide oscillator clock by ten module, what do I do now?...

13 comments posted 19yrs

posted by <222>

13 comments posted 19yrs posted by <222>

incremental compiles in quartus

We just purchased the full version of Quartus II (version 6.0) because it has the ability to perform incremental recomp...

1 comments posted 19yrs

posted by dt

1 comments posted 19yrs posted by dt

FX12 ethernet resource usage

Hi, I'm working on a design with V4 FX12 and gigabit rgmii PHY. To me it seemed obvious to use plb_temac and hard_temac...

4 comments posted 19yrs

posted by jetmarc

4 comments posted 19yrs posted by jetmarc

Announce: XDLAnalyze v1.1 and colorized_signals (for ModelSim) v1.1

I thought that some people on this newsgroup might be interested in two small hacks I've written recently: ------------...

3 comments posted 19yrs

posted by ehliar

3 comments posted 19yrs posted by ehliar

OFFSET Constraining a Signal behind a DCM?

Hi, I have a design, where I want to interface an ADC (250 MHz) to a Spartan-3E. The clock from the ADC enters the FPGA...

0 comments posted 19yrs

posted by cw

0 comments posted 19yrs posted by cw

unpredictable FPGA behaviour

Hi there, I apologize for the unspecific subject, but for me it is like that. I am working on an FPGA project which con...

3 comments posted 19yrs

posted by johannes.hausensteiner

3 comments posted 19yrs posted by johannes.hausensteiner

VHDL CODE FOR SDRAM IN SPARTAN 3E

Does anyone try to read values from sdram without the use of Microblaze?. It is simple to read/write values in ddr sdra...

3 comments posted 19yrs

posted by pbantunez

3 comments posted 19yrs posted by pbantunez

solder mask for fpga dissipation

Hi guys, I have to produce a PCB with a couple of FPGA on it and I was wondering if the solder mask right under the FPG...

10 comments posted 19yrs

posted by alessandro.basili

10 comments posted 19yrs posted by alessandro.basili