Spartan 3E Starter Kit Woes

Hi Dave,

I have about the same problem. DDR SDRAM on opb_ddr controller does not work. We have 3 rev.D boards and 2 fail memory tests. Actually we had 2 boards and onyl one worked, then I got one extra as a waranty. This extra does not work either. So if any has a good (proven!!) memory tester I would be happy to make some more tests. Otherwise some explanation from Xilinx guys would do.

Cheers,

Guru

Dave wrote:

Guru schrieb:

Hm

I wonder - if there are so many issues with DDR on the 3E starterkit how reliable will be the DDR2 memory on the new Spartan-3A kit?

Antti

DDR2 is simpler than DDR.

--
Ben Jackson AD7GD

http://www.ben.com/

NO WAY

I have plenty of boards with DDR memories on them, and all they work and I dont recall having problems DDR memory controllers

and with all DDR2 boards I see trouble...

xilinx recommends speed grade -12 for Virtex-4 DDR2 200mhz solution. getting DDR2 working with spartan-3, well doable I guess, but I would be glad to see my problems with Virtex-4 based board solved first before I belive Spartan-3 DDR2 solution is easy e.g simpler as DDR

maybe its only with Xilinx DDR2 solutions so, cant say as I dont have any lattice or altera DDR2 boards

Antti

Antti, I've got 4 banks of QDR-2 RAM working reliably at a 200 MHz clock rate with a Virtex4SX55-10 on a custom board. The interface uses the idelays and training. We had no problems bringing it up. The interface is not the Xilinx DDR IP discussed in the app notes though. The board design has to be done carefully in regards to signal integrity.

sure, I get DDR2 200mhz also working (V4 speed -10), but occasionally there are board related issues and there are also fpga timing issues with -10 speed grade.

if the idelay-+training works OK, and the board is really carefully designed then there are no real issues with DDR2, but so far when working with not so carefully designed boards and Xilinx IP cores

• OPB_MCH_DDR2

• PLB_DDR

• MPMC2

• MIG then there are defenetly issues getting things working at 200mhz (or meet fpga timings)

BTW, I do not have seen issues related to idelay, eg reading is ok but mostly errors are of type that 8 bits are not written, eg like one DQS is gone lost or something, from x16 device 8 bits are written and 8 bits hold old value, and readback is same many time, eg write succeeded but only to one half of the chip. this is with MPMC2 design that is on the board to meet the timing, and worst delay is in one DQS path so I am not sure if the problem is fpga timings or pcb layout

Antti

Well, first off the signals *must* be registered at the IOB or all bets are off. You need pretty consistent timing across all the IOBs, AND the pcb traces need to be matched for delay. The timing across the IOBs is pretty easy to get consistent if you register the IOBs (I know you already know that). Check the spec for the memory to see if the DQS edges need to be aligned with the write data edges or aligned with the data centers. I can never remember which it is, but somewhere along the line you wind up using a 90 degree clock to make the timing all work out. I'm not sure the Xilinx IP has that right or not. If your worst case delay on the board is one one of the DQS paths, it is possible the DQS is arriving too late to properly validate the write data.

signal *ARE* registered in IOBs, the worst case delay is in one of the DQS paths between

200MHz and 200MHz_90_degree clocks timing analyzer says 0 LUT levels and still doesnt meet the timing!

but the thing is not properly validatin the data, I mean threre is not the case that wrong data gets written, there is no write at all!

it is temperature dependant, after power up less errors, within few minutes more the error is that 8 bits do not get written, eg they hold old data like write never happened, while the other 8 bits in the same chip work all the time. its also not DM related i have checked that the same board works at lower DDR2 clock

what is a small puzzle is the fact that xilinx does not use DIFFerential I/O primitives for the DDR2 core (not at least in MPMC2) but that sould also possible cause only reading errors if the single ended DQS calibrate is not perfect and I have no read errors

Antti

Antti, check the relationship between DQS and the address and bank selects. sounds like the address/BS lines may not be meeting the setup or hold to DQS so the write is going somewhere else or getting blocked. As I recall, the xilinx reference design had the address out clocked by the wrong clock (270 degree vs 0 degree).

You might have to hand place the FF's going from 0 to 90 degree, or possibly duplicate registers if you have the crossing going to more than one destination. All of the current parts are capable of a 1.25ns connect between ff's, BUT, you have to have fanout of 1 and good placement to make it work out in the slower parts.

I had to use the differential DQS signalling to get DDR2 going on a V4FX100 board with 512mbit Micron DDR2. Without them I saw issues like you describe - 8 bits of a word failing here and there. I don't remember if it was write failures or read failures.

Note there's a typo in the mch_opb_ddr2 MPD file (EDK8.2 all service packs) that makes it impossible for BSB-created platforms to connect the DQSn signals correctly. Plus, BSB's DDR clocking structures leave a lot to be desired - you always need to rework them.

Cheers,

John