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PLL minimum input clock frequency

Hello all,

I would like to multiply by 4 a USB chip 12MHz clock. The phase shift is not important.

I cannot use LatticeXP PLL because minimum input clock frequency is 25MHz.

There is a way to work around this problem? I would like to save space and money avoiding an external oscillator.

Thanks,

Dan.

Reply to
Ndf
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I see two possibilities:

1) Cheat a little bit (assume that 24 MHz works in most cases) and double the clock input using LUT delays (and hope it's close enough to 50% duty cycle for this to work).

2) Add an external PLL frequency multiplier chip. ICS has some small (8-pin SOIC) cheap (cheaper than a crystal oscillator) parts that work at this frequency. ICS570B comes to mind...

Reply to
Gabor

Hi Dan, Gabor's blinkered ideas would work. However, they're not as much fun as accelerating the LatticeXP PLL to about 0.8773 of the speed of light. If you do that, the stationary oscillator appears to the PLL to be going at 25MHz. IME, this method involves messing around with enormous gravitational fields at event horizons, so watch out for evil red robots. HTH, Syms.

Reply to
Symon

you

25MHz.

fields

Thanks,

Unfortunately I'm not implicated on astrophysical research but I'll keep that on mind.

Dan.

Reply to
Ndf

Just use a crystal or resonator, not an oscillator. They are small and under a buck in small quantities. Use the Lattice to provide the gain and 180 degree phase shift required to sustain oscillation.

Jay

Ndf wrote:

Reply to
kayrock66

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