Guys, In a recent thread here on VAF we learnt, more or less, that a large part of the Virtex-4's Cpin of 10pF is due to the large output FETs needed to drive HSTL IV at 48ma.
Does the CCLK pin have this problem? If not, where do I obtain an IBIS model representative of the CCLK input?
UG071 recommends simulating CCLK as an "LVCMOS_P12" which doesn't exist in the IBIS file. Of course all the other models include the "Cpin of death". Thanks, Syms.