Field-Programmable Gate Arrays

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timing constraints properly setup

Hi, I am wondering if I wrote the timing constraint properly. I have 2 clocks (clk, phy_rx_clk) coming in from the outs...
0 comments posted 19yrs
posted by axr0284
0 comments posted 19yrs posted by axr0284

dynamically created blockRAM contents?

I have some Verilog code that generates an array of blockRAMs to any dimensions that I want. For example, if I set LENG...
5 comments posted 19yrs
posted by matt.fischler
5 comments posted 19yrs posted by matt.fischler

Spartan3E minimum clock-to-output (hold time)

I've been looking all over but have been unable to find any numbers for minimum clock-to-output propagation delay for S...
8 comments posted 19yrs
posted by larthe
8 comments posted 19yrs posted by larthe

Altera Cyclone II die revision?

from the Cyclone II errata sheet: The die revision is identified by the alphanumeric character (Z) before the fab code...
1 comments posted 19yrs
posted by manfred.balik
1 comments posted 19yrs posted by manfred.balik

ISE 8.2sp3 clobbering source file timestamps?

Against my better judgment, I tried using 8.2sp3 again tonight by converting and building an older, working 6.3 project...
2 comments posted 19yrs
posted by brimdavis
2 comments posted 19yrs posted by brimdavis

LatticeMico32 Problem

All, I am trying to run through the LatticeMico32 Tutorial from Lattice. Using 6.1.1 version LatticeMico32 System. I fo...
2 comments posted 19yrs
posted by jceven
2 comments posted 19yrs posted by jceven

Unconnected Blocks??

I keep getting the following warning from ISE: FF/Latch (without init value) have a constant value of 0 in block . FF/L...
0 comments posted 19yrs
posted by ian.peikon
0 comments posted 19yrs posted by ian.peikon

Virtex 4 FIFO question

The read and write signals have to be set one clock cycle before the action right? If I do the following, will it read t...
5 comments posted 19yrs
posted by null
5 comments posted 19yrs posted by null

measure setup and hold time

Hi I am currently working on a RGMII interface using the SPARTAN 3E FPGA. I have 1 clock pin (phy_rx_clk) feeding into...
6 comments posted 19yrs
posted by axr0284
6 comments posted 19yrs posted by axr0284

[XST 8.2.3] DSP48 inference multiply/add

hey, i have this piece of code where i want to use the multiply/add functionality of the DSP48 slice of a V4, i want to...
8 comments posted 19yrs
posted by tim.verstraete
8 comments posted 19yrs posted by tim.verstraete

DC timing violation, what to do first?

Hi all, I am new to Synopsys DC. And I have a basic problem. When I find timing violation in DC report, what shall I do...
9 comments posted 19yrs
posted by zhushenli
9 comments posted 19yrs posted by zhushenli

FPGA ROUTING

Hi everyone: I am new to FPGA and looking for a possible topic on FPGA routing algrithm. I read some classic articals i...
6 comments posted 19yrs
posted by ryan1219
6 comments posted 19yrs posted by ryan1219

Mapper using wrong EMAC with PowerPC in V4FX60

This is a V4FX60 design using one of the PowerPCs and one of the EMACs. The mapper uses the EMAC that has hard connecti...
1 comments posted 19yrs
posted by dcaulfield
1 comments posted 19yrs posted by dcaulfield