Anyone seen eASIC?

Has anyone here seen (or better yet, used) eASIC?

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It seems to be an FPGA programmed using a laser (so not really "F" PGA). Of course, this means it isn't re-writeable. Claims to be price competitive to FPGAs (even in small quantities).


Reply to
David R Brooks
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Per their website, they have 5 members of their 90nm technology, with basic fabric clock speed of 350 MHz. They offer a version with embedded ARM processor, too.

They do not have a 65nm product offering (yet). The Xilinx 65nm V5 line has a fabric which runs to 550 MHz (along with all the stuff that has to run with it).

The V4 line has all 17 parts shipping. The V5 line has all 6 LX parts in ES now, and all 6 LXT ES is just starting. That is 12 family members in the logic specific family, alone. Then you add the SX, SXT, FX, FXT...

They do not have the following hardened macros: MGTs DSP blocks TEMACs PCIe PPCs (plural, as in two IBM Power PC's in the larger parts) APU etc. I would think that they would have a huge line of hard blocks to spice up their offering, but then that requires a massive support burden (so they don't?).

They do not have domain specific families, such as logic, digital signal processing, or high speed serial IO/embedded processors (basically the LX, SX and FX mix we offer).

They do not offer a lower performance, cost reduced option line (Spartan), nor is there any offering to immediately reduce costs (like our EasyPath-tm).

They (claim) offer "ASIC" like power (as in very low static power, but since I have to register to read their datasheet, I can't verify that). They do offer fast turnaround (once you know it works). They do have smaller die (fewer transistors, cost per die are low).

I would be concerned about their SEU tolerance, as 90nm ASIC are at about 1000 FIT/Mb or M gates. That puts their largest device at 10 years between failures from SEU's (compared with >50 times that number for the comparable V5 part, or greater than 500 years MTBFF).

So, nice line, looks useful. How does it compare/compete with a re-programmable "latest and greatest" FPGA Family? That is up to you, the engineers who have the applications.


David R Brooks wrote:

Reply to
Austin Lesea

Without having seen the line information, but having seen such types of announcement in the past I would ask:

Is there true characterisation data?

a. IO b. IOBuf delays c. Pin details d. (Most important) Icc vs. specific implementations.

I have yet to see one of these parts compete properly on power and cost against the two competitors -> FPGA for effective cost and flexibility

-> true ASIC *or* controller for low power (no offense, but FPGAs just can't compete in the really low power domain).

I'll have a look tomorrow



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