Spartan3E minimum clock-to-output (hold time)

It seems that i (once again) didn't do enough of STFW before I posted. There is a thread (Best Case Timing Parameters) covering this topic. The conclusion seems to be to use 1/4 of the max value, except when using DCMs, where this will be too optimistic. In my case, I seem to be OK following this rule.

I still think there ought to be some data in the specs about this, as many external components (SDRAMs, DSPs etc.) require a non-zero hold time.

/Lars

Hi Lars, I'm sure you know that you can use the DCM to choose whatever phase shift of your clock you need. (Provided you meet certain frequency constraints) HTH, Syms.

Lars,

We had been given a similar number by Xilinx. We, too, thought that they meant that the minimum clock-to-out would be 25% of the maximum. However, when we were discussing this recently with them they said, "No, we mean a

25% decrease in clock-to-out with respect to the maximum."

So, now I'm confused, again.

Bob

Well, anyone stating that the delay would only vary between 75% and

100% of the maximum over process, temperature and voltage would get me suspicious... From my previous work with ASICs i recall a huge spectrum of delay from min to max, so 25%-100% seems much more plausible to me. That also seems to be the conclusion of the other post i found, and fits my original "gut feeling" guess, so I beleive I will stick with that.

/Lars

Additionally, the 25% quoted value has been offered as 25% of the fastest speed grade, not necessarily the speed grade used. I've seen 40% used elsewhere for other things.

There's also for some families - and I think the Spartan-3E got this status within the last several months - there's an option in Timing Analizer for a speed grade of "minimum" which will give the guaranteed minimum propagation delay values for the device. I'd suggest running Timing Analyzer on your design with the "minimum" speed grade option to see if the numbers come up with the appropriate values. From here you could decide if the DCM fixed phase shift is warranted.

- John_H

I have been looking for this also. Best thing to do is use the timing analyzer on an existing design. The minimum clock to output delay is used to calculate (IIRC) the hold timing.

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The accepted definition is: 25% of the max value as it is specified for the fastest speed grade. (If the max delay for the fastest speed grad is 4 ns, then the min value of that parameter for all speed grades is "no shorter than 1.0 ns") Assuming min to be "75% of max" is utter nonsense. Why the wide range? It covers temperature changes, Vcc changes, and processing variations, and also testing guardbands. All of this in the worst-case direction. Also; While max delays are tested, min delays are usually not testable, and must be "guaranteed by design, or by characterization". Luckily, a synchronous design is not concerned about min delays inside the chip. Memory interfaces often are sensitive, and ask for careful and creative design methodologies. Peter Alfke, Xilinx Applications

is use the timing

is use the timing

...and for more precise numbers on internal and external timing. Which brings me to the question: how does the Xilinx timing analyzer determine the minimum delay? Does it use 25% of fastest max. value or does it use worst case delays obtained by measurements and simulation?

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