Virtex 4 FIFO question

By the way I'm using the latest coregen FIFO generator. My question is, using the code above, will TEST be set to the fifo out byte and the end of the clock cycle?

right? If I do the >following, will it read the first FIFO byte?

the code above, >will TEST be set to the fifo out byte and the end of the clock cycle?

Are you writing in Verilog or VHDL? You need to show some more code. Are both of these things happening on the same posedge clk? If so you will most certainly miss the first piece of fifo out. Remember to think of these things in terms of hardware. There is a rising time for every signal. For instance when you say RD_EN

Also, I assume you are using Xilinx ISE for synthesis, etc. If all else fails, do some simulation for a better idea of what is going on. I can not stress how helpful this is.

Hope this helps.

Best, Ian

That's not my recollection. It seems to me as soon as you do your first write enable, data will be available at the output some clock cycles later. It's better to think of the RD_EN as a GET_NEXT signal, rather than a READ.

Brad Smallridge AiVision

Brad, what you describe is true in FWFT (first-word-fall-through) mode. In NORMAL mode, RE is required to even see the first word at the output.

The difference between the two modes (available in all Virtex-4 and Virtex-5 chips) is only relevant for reading the very first word that had been written into an empty FIFO. Afterwards, RE gives you the next available word, as you descibe it, and this behavior is then independent of the mode setting.

I envision the read operation in FWFT as "push out" and NORMAL as "pull out". The difference is subtle, and important only for operation around the EMPTY situation. Peter Alfke, Xilinx Applications