dynamically created blockRAM contents?

If you use VHDL, you can initialize block RAMs during synthesis. Check the "Initializing RAM" section in XST User Guide for examples.

Cheers, Jim

matteo wrote:

I can infer blockRAMs and initialize their contents with a file using the $readmemh system task from an initial block. The problem now is how do I dynamically load a different file based on the parameters that get passed from an upper module? The syntax is

initial $readmemh("data.txt",Mem,0,7);

where 0 is the start address and 7 would be the end address if the depth was 8. Say I have a set of files for different blockram contents: data0.txt data1.txt data2.txt

the # comes in as a parameter. Is there a way that I can convert it to a string?

Matt

Does this help?

Is there some reason why the code that generates the initial contents is written in Ruby? More to the point, is there some reason that this Ruby program can not be converted to VHDL or Verilog bundled up as a function that will return the memory contents?

Kevin Jennings

What I've found is that in Verilog, what gets passed in as module parameters has to be a constant. I wanted to use genvar's but that is not allowed. The workaround was to write another Ruby script that would generate the Verilog code itself. Instead of using the generate statement I pre-generate each module with Ruby. This creates a large Verilog file but the parameters are now constant and the synthesis tool is happy.

messagenews: snipped-for-privacy@51g2000cwl.googlegroups.com...

code that generates the initial contents is