Hi I am currently working on a RGMII interface using the SPARTAN 3E FPGA.
I have 1 clock pin (phy_rx_clk) feeding into a DCM and 2 DCM output clk0 and clk180 being used in my design. There is also an external module which I have no control over that will be sending DDR data and clock with the data have a minimum setup time of 1.4 ns and minimum hold time of 1.2 ns.
I need to measure the setup time of the data when it reaches the first flip flop of the DDR which is found in the IOB itself.
So I setup the constraint to have 2 ns setup time wrt the input clock called phy_rx_clk Now the timing analyzer tells me that it actually needs a setup time of
3.9 ns and I am wondering why it needs such a long setup time.Wouldn't the DCM introduce some delay in the clock line wrt to the data line thus reducing the setup time.
Is there anyway to decrease this setup time to what I need.
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- COMP "rgmii_rx_ctrl" OFFSET = IN 2 ns BEFORE COMP "phy_rx_clk" HIGH | Requested | Actual | Logic | Absolute |Number of Levels | 2.000ns | 3.928ns | 0 | -1.928ns | 2
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Thanks for any answer. Amish