measure setup and hold time

Hi I am currently working on a RGMII interface using the SPARTAN 3E FPGA.

I have 1 clock pin (phy_rx_clk) feeding into a DCM and 2 DCM output clk0 and clk180 being used in my design. There is also an external module which I have no control over that will be sending DDR data and clock with the data have a minimum setup time of 1.4 ns and minimum hold time of 1.2 ns.

I need to measure the setup time of the data when it reaches the first flip flop of the DDR which is found in the IOB itself.

So I setup the constraint to have 2 ns setup time wrt the input clock called phy_rx_clk Now the timing analyzer tells me that it actually needs a setup time of

3.9 ns and I am wondering why it needs such a long setup time.

Wouldn't the DCM introduce some delay in the clock line wrt to the data line thus reducing the setup time.

Is there anyway to decrease this setup time to what I need.

------------------------------------------------------------------------------------------------------

  • COMP "rgmii_rx_ctrl" OFFSET = IN 2 ns BEFORE COMP "phy_rx_clk" HIGH | Requested | Actual | Logic | Absolute |Number of Levels | 2.000ns | 3.928ns | 0 | -1.928ns | 2

------------------------------------------------------------------------------------------------------

Thanks for any answer. Amish

Reply to
axr0284
Loading thread data ...

------------------------------------------------------------------------------------------------------

------------------------------------------------------------------------------------------------------

If your timing report states a negative value for hold time (and assuming that this is not needed), you can trade (at least some) if this time into less setup time.

Most likley the tools have inserted some input delay in the IO block to assert a negative hold time for your input. This is normally not needed when working with DCMs. Check IBUF_DEALY_VALUE and IFD_DELAY_VALUE in the constraints guide. A quick check is to open the design in FPGA-editor and have a look inside the IO block to see what values have been assigned to these parameters.

/Lars

Reply to
Lars

------------------------------------------------------------------------------------------------------

------------------------------------------------------------------------------------------------------

Reply to
axr0284

ll

of

ta

------=AD---------------------------

GH

------=AD---------------------------

Yes you can! Have a look in the Spartan-3E data sheet, page 11. The delay to the interior of the FPGA can be set to the in 250 ps increments and the delay to the IO-block register in 500 ps increments from 0 to aprox. 5.8 ns.

/Lars

Reply to
Lars

will

me

rst

ck

e of

data

--------=AD---------------------------

HIGH

--------=AD---------------------------

to

ed

ve

Reply to
axr0284

Hi everybody, it may seem a little off topic, but during a discussion with my colleague about state machines we came across this name, and wondered when he lived and worked on his state machine theory. First thing was to search the net, but besides politics and genetics etc. there was not even his first name mentioned, not to speak of when or where he lived and worked.

Anyone has an idea/reference?

Thank you in advance Eilert

Reply to
backhus

Russian names are spelled differently in different languages, so... possibly Fyodor Andreevich Medvedev (1923?1994)

formatting link

Is this the guy?

I haven't found a whole lot online either,as you can see!

- Brian

Reply to
Brian Drummond

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.