Latest threads in Field-Programmable Gate Arrays

Question about partial multiplication result in transposed FIR filter

Hi, When I read a tutorial on FIR implementation on FPGA, I am not clear about "partial results can be used for many mu...

4 11yrs

rxjwg98

4 11yrs rxjwg98

What equivalent attribute in Xilinx IDE

Hi, I see an example on Xilinx FPGA with tool Synplify-Pro: attribute syn_multstyle : string; attribute syn_multstyle o...

0 11yrs

rxjwg98

0 11yrs rxjwg98

Can anybody knowledgeable on DisplayPort help me?

Hi, My DisplayPort project has hit a speed bump - so close yet so far! Is there anybody who knows DP and can can help m...

1 11yrs

mikefield1969

1 11yrs mikefield1969

I am getting errors when i run a systemC Code in edaplayground

Hi, I am getting below errors when i use systemc in edaplayground error: 'sc_sgnal' was not declared in this scope. I h...

3 11yrs

ecebharath

3 11yrs ecebharath

low-level vs. high-level

Hi, I use graphical high-level tools to design DSP stuff and generate RTL for it. It works for me, but I started to sus...

23 11yrs

e.v.filatov

23 11yrs e.v.filatov

How to understand obfuscated IP codes?

Hi, Good day to all. If suppose i received a HDL code for FPGA related design and it is obfuscated, how to understand i...

4 11yrs

108364

4 11yrs 108364

[JOB POSTING] Full-time FPGA/Hardware Engineer

kvm-tec electronic is a small company based in Austria. We are currently looking for another full-time engineer with FP...

0 11yrs

ajpkane

0 11yrs ajpkane

Why is this group so quiet?

I was just wondering... why is this group so quiet? With lots of interesting news like: Microsoft Extends FPGA Reach Fr...

25 11yrs

mikefield1969

25 11yrs mikefield1969

Re: Q: CPLD input mux structure

>> Hello, >> How are typical CPLD input muxen build up? > > (For other posters, a CPLD is a "complex programmable logic...

0 11yrs

klammerj

0 11yrs klammerj

Strange way to route design.

Hello, colleagues. I'm fixing issues of the design with many clocks and its interaction on Art ix7 FPGA. In order to mo...

4 11yrs

stebanoid

4 11yrs stebanoid

Picking the best synthesis result before implementation

Out of curiosity, I wrote a script to explore with different options in the Vivado software (2014.4), especially on the...

10 11yrs

kt8128

10 11yrs kt8128

fifo or sdram bug?

In our system a signal is passed through a couple of fifos inside FPGA and then onto external sdram to be read by appli...

30 11yrs

37480

30 11yrs 37480

FPGA board to interface with ADC (>10 GHz) and generate 5Gbps PRBS

Hello all, I am designing a circuit that requires a 10 GHz ADC and a FPGA to generate a 5 Gbps PRBS. I am not able to f...

0 11yrs

vivek.v80

0 11yrs vivek.v80

Finally! A Completely Open Complete FPGA Toolchain

I am very impressed. I was reading about Antti's incredibly tiny FPGA project board and saw a mention of a FOSS FPGA to...

59 11yrs

gnuarm

59 11yrs gnuarm

Free Lattice FPGA

I'm turning out a cupboard and have found 10 off Lattice LFECP10E-4FN256C - still sealed in dry packs. Location SW Scot...

0 11yrs

nospam

0 11yrs nospam

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