Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Image Compression in an FPGA
Someone is looking to generate compressed images in an FPGA to display graph data on a browser. Looking around the GIF, TIFF or PNG formats seem rather straightforward to implement. Anyone know of an...
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8 years ago
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Aligning symbols with IDELAY / ISERDES in Xilinx 7-series devices.
Hi, I'm working in Artix-7 and I've got a workable way to adjust the bitslip an d IDELAY tap settings to lock onto an incoming TMDS encoded stream, but is there a better way? Currently I count the...
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8 years ago
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Special issue of Xcell Journal
Hey folks, my team just posted a new issue of Xcell Journal. Here is the link to the pdf: Here is the link to the digital magazine version: Cheers, Mike Santarini
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8 years ago
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Calculate dynamic power at fmax in Quartus
Dear All, Why dynamic power after compilation complete equal to zero, any idea how can I calculate dynamic power at max freq in Quartus? Regards --------------------------------------- Posted through
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8 years ago
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Dynamic Array in VHDL
want to use dynamic range of array , so using "N" for converting an incoming vector signal to integer. Using the specifc incoming port "Size" gives me an error, while fixed vector produces perfect...
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8 years ago
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Distributed ram timing qurry
I have several fifos that are small and implemented as distributed are some timing violations reported on paths between source register of fifo control signals(e.g. read signal) and fifo data output....
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8 years ago
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What's the name of this circuit?
Hi, I need to design a sub-module with 128-bit input and output stream interfaces (4 DWORDs/cycle) which can split the stream at arbitrary DWORD boundaries. Example input: DW3 DW2 DW1 DW0 DW7 DW6 DW5...
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8 years ago
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Installation of Vivado on Debian Linux on x86_64 machine
Hi, When I try to install Xilinx Vivado on 64-bit x86_64 machine, I get the following error: $ ./xsetup ERROR: This installation is not supported on 32 bit platforms. The reason is, that xsetup...
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8 years ago
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SVF test vector injection - generating SVF files
Good morning, I was trying to run some test vectors on an ATF1504ASVL_A44 CPLD. Even found some BSDL files on the net(no Idea if they're correct, tho'). I have vectors like this: V0001...
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8 years ago
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Speed of GTX transceivers in Kintex 7 in FBG package?
Hi, I have seen contradictory data about speed of GTX transceivers in Kintex 7 in FBG packages: 1. The datasheet ( , page 54 ) states that the maximum speed is 6.6 Gb/s 2. The answer record state s...
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8 years ago
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Conditional Interpretation of VHDL
I have a small project that produces a clone of the "BABY" computer at MOSI. I want to be able to produce two versions of the code, one which displays on a VGA screen and another which uses a...
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8 years ago
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Free Webinar: Overcome the challenges of powering FPGAs
Join UBM and Tech Online next week for a free webinar: Overcome the challenges of powering FPGAs. June 25th 11:00am PST/2:00pm EST An FPGA typically needs three or more voltage rails, each with a...
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8 years ago
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Energy efficiency of FPGA vs GPU vs CPU
This survey paper published in ACM Computing Surveys 2015 compares GPU with FPGA and CPU on energy efficiency metric. Most papers reviewed in the surv ey report that FPGA is more energy efficient than...
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8 years ago
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PCIe card with FPGA and DAC
I got a call from a really nice guy who has a tiny company in the Bahamas. Our gear is too expensive for his application, but it could be done with a PCIe PC-plugin board that has an FPGA and a fast...
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8 years ago
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Open/Free HLS weapon of choice ?
Hello all, I would like to know which open or free HLS (High Level Synthesi s) tools are gaining widespread use, or are more likely to survive, because at the time there seems to be too many, and the...
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8 years ago
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