Field-Programmable Gate Arrays

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What equivalent attribute in Xilinx IDE

Hi, I see an example on Xilinx FPGA with tool Synplify-Pro: attribute syn_multstyle : string; attribute syn_multstyle o...
0 comments posted 10yrs
posted by rxjwg98
0 comments posted 10yrs posted by rxjwg98

Can anybody knowledgeable on DisplayPort help me?

Hi, My DisplayPort project has hit a speed bump - so close yet so far! Is there anybody who knows DP and can can help m...
1 comments posted 11yrs
posted by mikefield1969
1 comments posted 11yrs posted by mikefield1969

low-level vs. high-level

Hi, I use graphical high-level tools to design DSP stuff and generate RTL for it. It works for me, but I started to sus...
23 comments posted 11yrs
posted by e.v.filatov
23 comments posted 11yrs posted by e.v.filatov

How to understand obfuscated IP codes?

Hi, Good day to all. If suppose i received a HDL code for FPGA related design and it is obfuscated, how to understand i...
4 comments posted 11yrs
posted by 108364
4 comments posted 11yrs posted by 108364

[JOB POSTING] Full-time FPGA/Hardware Engineer

kvm-tec electronic is a small company based in Austria. We are currently looking for another full-time engineer with FP...
0 comments posted 11yrs
posted by ajpkane
0 comments posted 11yrs posted by ajpkane

Why is this group so quiet?

I was just wondering... why is this group so quiet? With lots of interesting news like: Microsoft Extends FPGA Reach Fr...
25 comments posted 11yrs
posted by mikefield1969
25 comments posted 11yrs posted by mikefield1969

Re: Q: CPLD input mux structure

>> Hello, >> How are typical CPLD input muxen build up? > > (For other posters, a CPLD is a "complex programmable logic...
0 comments posted 11yrs
posted by klammerj
0 comments posted 11yrs posted by klammerj

Strange way to route design.

Hello, colleagues. I'm fixing issues of the design with many clocks and its interaction on Art ix7 FPGA. In order to mo...
4 comments posted 11yrs
posted by stebanoid
4 comments posted 11yrs posted by stebanoid

fifo or sdram bug?

In our system a signal is passed through a couple of fifos inside FPGA and then onto external sdram to be read by appli...
30 comments posted 11yrs
posted by 37480
30 comments posted 11yrs posted by 37480

Free Lattice FPGA

I'm turning out a cupboard and have found 10 off Lattice LFECP10E-4FN256C - still sealed in dry packs. Location SW Scot...
0 comments posted 11yrs
posted by nospam
0 comments posted 11yrs posted by nospam

Image Compression in an FPGA

Someone is looking to generate compressed images in an FPGA to display graph data on a browser. Looking around the GIF,...
8 comments posted 11yrs
posted by gnuarm
8 comments posted 11yrs posted by gnuarm