Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

Found: an FPGA with internal tri-states

In has been mentioned here a few times that there are no FPGAs with internal tristates. However, surfing around somewha...
12 comments posted 10yrs
posted by akuktin
12 comments posted 10yrs posted by akuktin

Quad-Port BlockRAM in Virtex

I think I need a quad-port blockRAM in a Xilinx V7. Having multiple read p orts is no problem, but I need two read port...
19 comments posted 10yrs
posted by kevin.neilson
19 comments posted 10yrs posted by kevin.neilson

DC Blocker

Hi all, I need to implement DC blocker in FPGA. Data samples are coming at every clock cycle. My original idea was to i...
23 comments posted 10yrs
posted by 108118
23 comments posted 10yrs posted by 108118

Interfacing ADS7230 ADC to Altera FPGA

Hi all, I want to implement an ADC Interface for an ADC - ADS 7230 (TI) in VHDL. I am not very familiar with ADCs to im...
1 comments posted 10yrs
posted by 109678
1 comments posted 10yrs posted by 109678

error Xst:899

I am receiving this error in xilinx ERROR:Xst:899 - "../../rtl/dff.v" line 7: The logic for does not match a known FF o...
1 comments posted 10yrs
posted by 109354
1 comments posted 10yrs posted by 109354

Sum of 8 numbers in FPGA

How do I most efficiently add 8 numbers in FPGA? What is the best way to save LUTs? How is data width affecting LUT con...
9 comments posted 10yrs
posted by 108118
9 comments posted 10yrs posted by 108118

recovery/removal timing

Hi All, In Altera devices (at least) it is recommended that reset be applied to the async port of flips. It is also rec...
51 comments posted 10yrs
posted by 93737
51 comments posted 10yrs posted by 93737

Custom FPGA routing

1)Have an array of logic cells or programmable logic evenly spaced out. Need to have the space reserved for routing cha...
2 comments posted 10yrs
posted by 109234
2 comments posted 10yrs posted by 109234

System On Chip From Microsemi

I guess I stopped looking at the Microsemi products some time back. The SOC devices put out by Actel were ok, but the p...
11 comments posted 10yrs
posted by gnuarm
11 comments posted 10yrs posted by gnuarm

DDR* SDRAM modules for simulation

Hi all. Is there, somewhere, an open-source Verilog (or VHDL, but Verilog is preferred) module of a DDR1/2/3 SDRAM that...
6 comments posted 10yrs
posted by akuktin
6 comments posted 10yrs posted by akuktin

Xilinx Spartan2E options?

I have a product series that has mostly moved to Spartan 3A, but one member of the family is still using up boards made...
3 comments posted 10yrs
posted by jmelson
3 comments posted 10yrs posted by jmelson