Hi, I need to design a sub-module with 128-bit input and output stream interfaces (4 DWORDs/cycle) which can split the stream at arbitrary DWORD boundaries.
DW3 DW2 DW1 DW0 DW7 DW6 DW5 DW4 DWB DWA DW9 DW8
Example output (stream was split after DW4 and re-starts with a full 128-bit word):
DW3 DW2 DW1 DW0
- - - DW4 DW8 DW7 DW6 DW5
- DWB DWA DW9
Before I implement something naively in VHDL, I was wondering how this kind of circuit is called and whether there are any standard architectures for it. The application is, by the way, PCIe TLP splitting and header insertion.