I have several fifos that are small and implemented as distributed ram.There are some timing violations reported on paths between source register of fifo control signals(e.g. read signal) and fifo data output.
This raised some question in my head as how timing is assessed for such fifos (or SRL for that matter). A fifo or SRL chain uses luts plus output register. Wouldn't that mean there is inherently a long path to the output register or should we say it is long but not combinatorial? Is there anyway to improve timing in such designs like fifos or SRL chains.
Regards
Kaz
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