Latest threads in Field-Programmable Gate Arrays

Different Modelsim versions disagree in same backannotation!

Hi all! I am experiencing a very strange and rather frustrating problem while trying to run the same backannotated simu...

7 19yrs

jorgelagos

7 19yrs jorgelagos

TESTAPP_PERIPHERAL FAILED IN ETHERNET

Hi, I am tryint to include an ethernet app in my design, but always failed. So I try to probe the code example generate...

0 19yrs

pbantunez

0 19yrs pbantunez

Source Synchronous LVDS Design - Phase Shift in the Timing Analysis?

Hi, I plan to interface a 250MHz ADC with an Spartan 3E-1600. The ADC gives out 8 data lines and 1 clock line, all via...

2 19yrs

cw

2 19yrs cw

Xilinx website login problems

I wonder if thats only from Europe or is that something at Xilinx server, all login attemps time-out today :( Antti

7 19yrs

Antti.Lukats

7 19yrs Antti.Lukats

Generation of Divided-by-3 clock

Hi, I need to generate a 70MHz clock from 210MHz. Is there any way to generate it rather than using a DCM. Thanks, Sudhe...

10 19yrs

ksudheerkumar

10 19yrs ksudheerkumar

ARM AHBA 1Kbyte boundary issue

DEAR ALL, As I am a beginner in ARM AHBA bus protocol. I cant understand why AHBA bus need to limit 1Kbyte boundary? (A...

4 19yrs

kelvins.huang

4 19yrs kelvins.huang

Behavior of REV input in Virtex2 flops?

I'm trying to understand the behavior of the REV pin works on Virtex2 flops. The Virtex2 Pro/Pro-X data sheet (ds083.pd...

1 19yrs

neil.steiner

1 19yrs neil.steiner

Process on both edges

In vhdl is it possible to run a process on both edges of a clock? I tried running one if-statement on the rising edge, a...

4 19yrs

null

4 19yrs null

Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology

What are some of the considerations while migrating from a pure SW based bio-medical simulation to a HW based simulatio...

7 19yrs

writeanand

7 19yrs writeanand

PCI Card with FPGA

Hi, I am looking for a PCI card with an FPGA on it with reasonable capacity of gates (15 million gates). I need to use...

10 19yrs

sheikh.m.farhan

10 19yrs sheikh.m.farhan

Ethernet Interface

Is it possible to interface the Ethernet directly to the FPGA instead of the doing it through the Power PC processor or...

5 19yrs

aswingopalan

5 19yrs aswingopalan

Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use

Hi everyone, it happened to me that by chance I interrupted ModelSim not properly (to be honest I cannot say what happe...

4 19yrs

alessandro.basili

4 19yrs alessandro.basili

running applications from external memory

> Hello All, > > I figured out how to run an application from external memory in Xilinx. > I have EDK ver 8.2.01i and a...

7 19yrs

balsub123

7 19yrs balsub123

Clock Frequency

hey guys... can u please tell me a method to reduce the clock frequency of the FPGA using counters puneet

2 19yrs

psgandhi

2 19yrs psgandhi

interesting article FPGA routing field programmable nanowire interconnect (FPNI)

thought it was an interesting article...

3 19yrs

yttrium

3 19yrs yttrium

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