Field-Programmable Gate Arrays

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Synchronizing four phase-offset clock domains

I'm working on modifying a design in order to meet my needs and am having trouble coming up with a workable soltuion. I...
0 comments posted 19yrs
posted by john.windish
0 comments posted 19yrs posted by john.windish

Setup time path on V4 SX w/ IDELAY

I have the following path in an IOTILE: IBUFDS --> IDELAY (IOBDELAY_TYPE => "FIXED", IOBDELAY_VALUE => 0) --> FDC I hav...
1 comments posted 19yrs
posted by killerhertz
1 comments posted 19yrs posted by killerhertz

about XAPP028

I am find this document when search information about PLL. There three phase detector circuts. I simulate its in MAX+, b...
0 comments posted 19yrs
posted by axalay
0 comments posted 19yrs posted by axalay

Two newbie Chipscope questions

Hi, I am new to using Chipscope, I've read the manual and lots of tutorials in the www and threads in this newsgroup. I...
1 comments posted 19yrs
posted by kronkarp
1 comments posted 19yrs posted by kronkarp

four phase clock using DCM with xilinx FPGA

Hi, I need to generate four clocks with DCM in VIRTEX4. The frequency is 312MHz. I can't get any output from clk_90 and...
7 comments posted 19yrs
posted by chenyong20000
7 comments posted 19yrs posted by chenyong20000

Digital Filter and external PLL (VCO)

I am generate 2.048 MGz with jitter ~5ns if FPGA. I need to reduse jitter and vander using the digital filter. Tell me...
4 comments posted 19yrs
posted by axalay
4 comments posted 19yrs posted by axalay

Constraining Multiple clock design

Hi all, I'm using Mentor Graphic tools to synthesize my design (Leonardo Spectrum: ASIC and Precision RTL: FPGA). The p...
1 comments posted 19yrs
posted by umrtech
1 comments posted 19yrs posted by umrtech

Registered?

Hi, I'm trying to simulate Error Corection Coding (Reed-Solomon) ip core with Xilinx Spartan FPGA as the target. Using...
2 comments posted 19yrs
posted by ian.shee1
2 comments posted 19yrs posted by ian.shee1

Verifying a Bidirectional Data Bus

I have had reasonable success verifying some designs using behavioral verilog and modelsim. I seem to have trouble with...
0 comments posted 19yrs
posted by portisi
0 comments posted 19yrs posted by portisi

EDIF format

hi, where can i find a description of the edif format. www.edif.org doesn't have the syntax regards, quad
9 comments posted 19yrs
posted by fyp.quadruples
9 comments posted 19yrs posted by fyp.quadruples

benchmarks for vhdl

Hello all, I would like to know if there are benchmarks available for testing vhdl codes. I need TCP/IP packets input to...
0 comments posted 19yrs
posted by dhruvakshad
0 comments posted 19yrs posted by dhruvakshad

ISE 9.1i and partial reconfiguration

Hi all! ISE 9.1i is finally out! I read the marketing papers but didn't find any word about partial reconfiguration supp...
4 comments posted 19yrs
posted by taileb.mehdi
4 comments posted 19yrs posted by taileb.mehdi

PowerPC_DDR_controller

Has anyone use the PLB DDR controller for the PowerPC in the EDK 7.1? I have implented it in my design and it takes 150...
1 comments posted 19yrs
posted by
1 comments posted 19yrs posted by