# Clock Frequency

• posted

hey guys...

can u please tell me a method to reduce the clock frequency of the FPGA using counters

puneet

• posted

Use a DCM(xilinx) or PLL (altera), or keep the clock frequency the same and use clock enables to run this logic at a lower rate, or use a counter to reduce the clock frequency.

What are you trying to do?

snipped-for-privacy@gmail.com wrote:

• posted

"""Andrew FPGA =D0=BF=D0=B8=D1=81=D0=B0=D0=BB(=D0=B0): """

Example (in Verilog): Generate 8.192 (2.048 * 4) MHz from 19.44 MHz workin on 155.52 (19.44 *

8) MHz This metod generete parazitic jitter.

//=C3=8C=C3=AE=C3=A4=C3=B3=C3=AB=C3=BC =C3=B4=C3=AE=C3=B0=C3=AC=C3=A8=C3=B0= =C3=B3=C3=A5=C3=B2 =C3=A8=C3=A7 155.52 =C3=8C=C3=83=C3=B6 8.192 =C3=8C=C3= =83=C3=B6 //=C3=84=C3=AB=C3=BF =C3=BD=C3=B2=C3=AE=C3=A3=C3=AE =C3=AD=C3=A5=C3=AE=C3= =A1=C3=B5=C3=AE=C3=A4=C3=A8=C3=AC=C3=AE =C3=A2=C3=BB=C3=A4=C3=A0=C3=B2=C3= =BC 126 =C3=B0=C3=A0=C3=A7 10 =C3=AF=C3=A5=C3=B0=C3=A8=C3=AE=C3=A4=C3=AE=C3=A2 =C3=A8 130 =C3=B0=C3=A0=C3= =A7 9 =C3=AF=C3=A5=C3=B0=C3=A8=C3=AE=C3=A4=C3=AE=C3=A2 //4 =C3=AB=C3=A8=C3=B8=C3=AD=C3=A8=C3=B5 9 =C3=AF=C3=A5=C3=B0=C3=A8=C3=AE= =C3=A4=C3=AE=C3=A2 =C3=A2=C3=BB=C3=A4=C3=A0=C3=A5=C3=AC =C3=AD=C3=A0 1-=C3= =A9, 64-=C3=A9,

128-=C3=A9 =C3=A8 193-=C3=A9 =C3=B0=C3=A0=C3=A7=C3=BB module divide_clk (RESET, iCLK, oCLK); input RESET; input iCLK;

output oCLK; reg oCLK;

reg [7:0] aCOUNT; //=C3=91=C3=B7=C3=A5=C3=B2=C3=B7=C3=A8=C3=AA reg [4:0] bCOUNT; //=C3=91=C3=B7=C3=A5=C3=B2=C3=B7=C3=A8=C3=AA =C3= =A8=C3=AD=C3=B2=C3=A5=C3=B0=C3=A2=C3=A0=C3=AB=C3=A0 9 =C3=A8=C3=AB=C3=A8

10 CLK

always @(posedge iCLK) begin if (!RESET) begin oCLK =3D 0; aCOUNT =3D 0; bCOUNT =3D 0; end //if else begin if (aCOUNT =3D 128 && aCOUNT

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