Behavior of REV input in Virtex2 flops?

Question

I'm trying to understand the behavior of the REV pin works on Virtex2 flops. The Virtex2 Pro/Pro-X data sheet (ds083.pdf, Module 2, Functional Description, Logic Resources -- page 36 in v4.5) states the following:

"When SR is used, a second input (REV) forces the storage element into the opposite state. The reset condition predominates over the set condition."

I'm not sure that I understand what that's trying to tell me. Is the following correct, or does "the reset condition predominates" mean something else?

Synchronous Mode:

Asserting SR forces state to the selected SRHIGH/SRLOW on appropriate clock edge.
Asserting SR and REV forces state to inverse of SRHIGH/SRLOW on appropriate clock edge.

Asynchronous Mode:

Asserting SR forces state to SRHIGH/SRLOW immediately.
Asserting SR and REV forces state to inverse of SRHIGH/SRLOW immediately.

For 4, is there some required timing relationship between SR and REV? Since REV apparently does nothing on its own, does it just need to remain asserted until SR gets deasserted?

Ed McGettigan · Accepted Answer

The SR pin takes precedence over the REV pin when asserted, so statements

2 and 4 above are incorrect. They should start with "Deasserting SR and asserting REV".

Both pins have a setup time to the CLK pin that must be met in synchronous mode to operate correctly.

Ed McGettigan

-- Xilinx Inc.

Behavior of REV input in Virtex2 flops?

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