Generation of Divided-by-3 clock

This is not a hard problem if you don't care about duty cycle. I'll leave that for you to logic out, but if you need 50% duty cycle then there are tricks.

Peter Alfke from Xilinx wrote an excellent article about clock dividers titled "Unusual Clock Dividers." It was published the Xilinx's Xcell Journal. I believe issue 33, but it appears Xilinx has gotten rid of that article as it's archives don't go back far at all anymore.

You could probably find it through some googling, but this brings up another point: Why would Xilinx remove it's archives? It's not like the material was dated.

That particular article has been of use to me several times. Peter wrote a great article. I'd like to see it come back.

-Arlen

K. Sudheer Kumar wrote:

Hi Peter,

Thanks for your suggestion. I would appreciate your providing me a copy of your article "Unusual Clock Dividers".

Sudheer.

Peter Alfke wrote:

sudheer schrieb:

dear Sudheer,

isnt goodle your friend too?

Antti

Stop whining and start searching! :-)

HTH, Syms.

Hi, I studied this article. It is very interesting, and the resources consumption is very low. For a general purpose, I think Anydivider can help. In this case, just enter "3", and then get the verilog code and the waveform. For more features, please visit

TAD

"Antti =D0=B4=B5=C0=A3=BA "

module clock_div3 ( clock_in, clock_out );

input clock_in; output clock_out;

reg clock_out; reg [2:1] d_pos; reg [2:1] d_neg;

always @ (posedge clock_in) case (d_pos) 2'b00: d_pos[2:1]

I see all these references to my old article in XCell magazine, and I enjoy the positive comments. But: In almost all cases, there is no need for 50% duty cycle. The natural 33/66% duty cycle of a simple divide-by-three circuit is acceptable, especially at such low frequencies as 70 MHz.

Here is one of the simplest implementations: Two flip-flops QA and QB, QA feeds the D-input of QB (shift register) The NOR of QA and QB feeds the D input of QA. This circuit also recovers from the illegal state of both QA and QB being High. Peter Alfke

Thanks to alll for sending their comments/Useful Links.

I'm getting worried about the phase misalignment of divided clock w.r.t the source clock because of combinational logic associated with the output.

I would like to welcome your suggestions/comments on this

Note: Duty cycle with 33%, 66% will not be worked out in our case, so badly I'm in need of clock with 50%dutycycle.

Thanks a lot once again, Sudheer.

K. Sudheer Kumar schrieb:

You could use pseudo dual-edge flipflops.

Ralf