Latest threads in Field-Programmable Gate Arrays

low speed USB interface for FPGAs

Hello all, I am a college student experimenting with VHDL and currently using the Spartan 3 starter kit. This particula...

4 19yrs

nugentoffer

4 19yrs nugentoffer

Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP

Hi, I m looking for differences between rocketio MGT and GTP (both architectural as well as the way they are used). plea...

5 19yrs

nagarajputti

5 19yrs nagarajputti

Xilinx ISE 8.2

I'm looking for POSITIVE feedback on Xilinx ISE. Yes i realize it has it problems, but It's free. So, I've been looking...

27 19yrs

bgshea

27 19yrs bgshea

Scrambling for Lattice SC

Hi newsgroup, is it possible to design some scrambling mechanism for Lattice SC FPGAs with some additional CPLD/FPGA ?...

0 19yrs

ALuPin

0 19yrs ALuPin

Xilinx doing a re-entry in non-volatile FPGA arena!!!

With Spartan-3AN is Xilinx making its entry in the non-volatile FPGA arena. I am glad that this can now be discussed in...

14 19yrs

Antti.Lukats

14 19yrs Antti.Lukats

Clock constraints

Hi, I will input a differential clock to DCM, how should I set contraints? Should I set constraint on IBUFGDS input or...

2 19yrs

chenyong20000

2 19yrs chenyong20000

what happened to modular design in ISE9

Hi, while Iwere reading some chapters of the new ISE9 Development System Reference guide I happened to notice that the...

4 19yrs

nix

4 19yrs nix

"Divide" a video line in two stripe

Here's my problem : A have a video module (that I can't really change), that outputs a 3840x2400 image, by outputing tw...

13 19yrs

SomeOne

13 19yrs SomeOne

Using demo IP libraries?

I'm trying to build one of the sample projects (ml403_emb_ref_ppc) that comes with the ML403. I'm running Platform Stud...

0 19yrs

zwsdotcom

0 19yrs zwsdotcom

How to exclude timing violations in Xilinx *.ucf file

Hi, I have 2 questions to ask for help. 1. My a project has a module outputing AD_OE signal. That signal drive 64 outpu...

0 19yrs

wtxwtx

0 19yrs wtxwtx

how to use register to save data

There are Matrix 4 by 4 R and Vector 4 by 1 B generated in Matlab. I transmitted these data to FPGA board. The 16 eleme...

6 19yrs

threeinchnail

6 19yrs threeinchnail

When do I need reset and clear?

The question is about the xc9500 familiy. I understand that if I need to connect a clock to the chip, I should use the...

0 19yrs

0 19yrs <shitsu>

system generator from Xilinx

Hello all, I just wanted to find out how good system generator software is? I can program in VHDL and would like to kno...

4 19yrs

nbg2006

4 19yrs nbg2006

project help

hi everyone I am doing a fpga based project for my engineering course completion. camera will be connected to the kit....

3 19yrs

shahmdk

3 19yrs shahmdk

digilent nexys vga glitches

Newbie problem: I get some nasty horizontal jitter on vga display controlled by a vga controller (see below) running on...

9 19yrs

corer

9 19yrs corer

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