With Spartan-3AN is Xilinx making its entry in the non-volatile FPGA arena.
I am glad that this can now be discussed in open, as WebPack 9.1 includes already support for S3-AN. So my speculations, about "Why S3-A if its not volatile" was justified, with the only difference that S3-A has 2 derivates, with and without integrated non-volatile storage.
Antti
you mean there is no need for PROM? it's sure convienient for customer. do they use Flash or EEprom ?
jet
Antti wrote:
jetq88 schrieb:
it looks like serial flash to the user logic, and it can be accessed after configuration.
Antti
Sounds interesting.. Antti, have you any idea of the size of the N.V. memory, and whether (as jet wrote) it can be used to store a configuration? I haven't gotten around to installing 9.1 yet, maybe i'll make it more of a priority. Ben
Any price indication for the XC3S50A-TQ144 part ..? and the rest? RoHS?
Only Avnet, NuHorizons listed as suppliers..
Will there be any more than 50k chips in non-bga package?
Antti,
See:
Answer Record 24332.
Sorry to keep everyone guessing, but we will announce when we are ready.
Austin
Austin Lesea schrieb:
Hi Austin,
I hope I havent said anything too much, I felt it is OK to let the cat out of sack, as the WP9.1 includes the S3-AN support files. And sure I know that for the actual release and full docs there is no public discussion until full release.
BTW the AR about ISE 9.1 and S3AN has date: 12/05/06 08:00:36 !? Kind of weird that this AR was filed before ISE 9.1 availability.
Antti
Antti,
No problem. We have to release our software on a regular schedule, so there is no holding it back.
I would caution that whatever is revealed in the software may be updated or changed in the future, so the recommendation to work with our FAEs (if you really want to use a product before its release) is still valid.
Austin
Are there any plans for a non-volatile version of the Spartan 3e?
Austin Lesea schrieb:
Huh. tnx.
I just pointed out to some info that is revealed by the WP 9.1, things that are to my understanding command knowledge as of today.
The fact that actual product release announce are not in sync with software updates is a bit confusing. For me at least, but I guess that explains why I failed so miserable on brainbench online examps for: "SCM: Software Configuration Management".
At the moment I can only say that S3AN looks like REALLY REALLY nice FPGA! A real nice one. And I can only whish that package options would include VQ64 DIP40 QFN48 ;) kidding. but really, a package with outline 8by8 mm or less would be really nice. Altera is currently leading in this regard the MAX II has 0.5mm 100 ball BGA with measueres 6by6mm !
thats a real dream package. ok, I can little relax the specs, S3AN in 8bx8 mm microFPGA would be close to a truedream as well.
Antti
radarman schrieb:
Rick, if you look at the datasheet of S3-A then you should be able answer your question yourself.
NO.
S3-A is re-engineered to have features needed for non-volatile on chip storage.
This is mainly the feature to self-reinit the a re-confiugration from random address and optionally from different configuration interface. That is S3A (and AN) is first Xilinx that can force itself to be reconfigured in an config mode defined by user app. S3E and V-5 have both limited multi-boot functionality S3-E can init "second config only in BPI mode" Virtex-5 can restart config from any user defined offset in same mode (eg cant over-ride mode pin setting) S-3A/N can restart config from user defined offsert in user defined mode.
from the above you can see that for sure, S3E will not have non-volatile version - it does not make sense.
Antti
So this is a dual-die release ? - makes it a fairly incremental advance, and perhaps able to give more illusion of security.
Will it cost less than an external multisourced SPI that follows the industry price curve ? - very unlikely.
Or maybe they chose to use more bond wires, for better load times, and usefull execute-from-flash speeds ?
With Soft CPU deployment more common, the config memory size is no longer as defined as it was, so matching the bundled EE to the users needs is a challenge.
-jg
CP132 package 6.5x6.5 mm for S3E/S3 is already there. See it on our Craignell modules here
The only thing with 0.5mm ball grids is the pcb technology you need to use to achieve a design. Getting the alignment correct in assembly is also fun.
As to S3AN it would be nice but may not be practical depending on the approach taken by Xilinx in implementing the loading mechanism. We will all have to wait until the marketeers are ready to show you more.
John Adair Enterpo> Austin Lesea schrieb:
John Adair schrieb:
John,
please read
or measure on your board CP132 is 8 by 8 the smallest kinda FPGA is today MAXII in true 6 by 6 (outer dimensions!)
but, well CP132 is package too :) Antti
Well I read the wrong dimenson. It's still bl**dy small. But if want to be totally accurate, and not in any way to ignore the significance of the part, Altera do describe the Max-II as a CPLD so I guess the 8x8 CP132 packaged S3E might be the smallest packaged FPGA.
John Adair Enterpo> John Adair schrieb:
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