How to exclude timing violations in Xilinx *.ucf file

Hi, I have 2 questions to ask for help.

My a project has a module outputing AD_OE signal.

That signal drive 64 output pins: AD(63 downto 0) 'Z');

Now AD_OE has timing violations.

In my design AD_OE signal is handled specially so that it should be excluded in timing violation tables.

After using ChipScope tool, I found that AD_OE generates 64 registers internally by Xilinx compiler: AD_OE_0, AD_OE_1, AD_OE_2, .. AD_OE_63.

The following equations are all wrong with Xilinx compiler: INST "m_t_statea/ad_oe" TNM = "PCI_OE"; INST "m_t_statea/ad_oe_0" TNM = "PCI_OE"; INST "m_t_statea/ad_oe" TNM = "PCI_OE"; INST "ad_oe_0" TNM = "PCI_OE"; INST "ad_oe" TNM = "PCI_OE";

From timing violation listing by using Xilinx Timing Analyzer, it shows

timing violations: M_T_StateA/AD_OE_0 (FF) ... M_T_StateA/AD_OE_15 (FF)

I copy those signals directly into *.ucf as above, all are compiler errors.

What should I do now?

How to set default timing violation count from 3 to any number for Xilinx Timing Analyzer?

Thank you.

Weng