Newbie problem: I get some nasty horizontal jitter on vga display controlled by a vga controller (see below) running on a digilent nexys board. It looks like all scan lines jitter relative to each other (couple of pixels left/right). The problem is worse on the first 1/16th of the screen and it is getting better below (still jitters on the bottom though).
Looking at the hsyncs via an oscilloscope shows that the pulses do actually slide left and right like crazy and are really unstable (10-20ns jitter).
I tried to look at the output of a production vga adapter and it looks more stable (do not jitter as much) and the edges of the pulses are much more "square" (raise time is much smaller). Another difference is with the voltage - nexys uses 3.3v and it looks like the vga adapter I tried has 5v output.
I looked all over the internet and it doesn't seem like anybody else has this problem. Have anybody tried to get a nice and stable picture via nexys vga? What am I doing wrong? Is it supposed to be that "imperfect"? How do I fix it?
The setup: - 100Mhz nexys builtin oscillator clock is fed into mclk input signal - Desired output 800x600 72Hz (50MHz pixel clock) - nexys vga (vga port + 12 resistors) is used (inserted into j8 slot)
-- variation of vga controller code (this is one of the ways
-- i tried library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga2 is Port( mclk: in std_logic; ssen: out std_logic_vector(3 downto 0); led: out std_logic_vector(7 downto 0); j8VGAR: out std_logic_vector(3 downto 0); j8VGAG: out std_logic_vector(3 downto 0); j8VGAB: out std_logic_vector(3 downto 0); j8VGASync: out std_logic_vector(1 downto 0)); -- - hs, - vs end vga2;
architecture Behavioral of vga2 is signal hCount: std_logic_vector (11 downto 0); signal hBlank: std_logic; signal hSync: std_logic;
signal vCount: std_logic_vector (20 downto 0); signal vBlank: std_logic; signal vSync: std_logic; begin -- count pixels process constant pixClocks: integer := 2; constant hMax: integer := 1040*pixClocks; -- line duration constant hWidth: integer := 120*pixClocks; -- hsync width constant hBack: integer := 61*pixClocks; -- line back porch constant hFront: integer := 53*pixClocks; -- line front porch
constant vMax: integer := hMax*666; -- frame duration constant vWidth: integer := hMax*6; -- vsync width constant vBack: integer := hMax*21; -- frame back porch constant vFront: integer := hMax*35; -- frame front porch begin wait until mclk = '1' and mclk'Event;
-- update horizontal counter if hCount = hMax - 1 then hCount '0'); else hCount