Hi newsgroup,
is it possible to design some scrambling mechanism for Lattice SC FPGAs with some additional CPLD/FPGA ? Unfortunately there is no integrated circuit included yet to protect the bitstream.
Thank you for your opinions.
Rgds Andre
Hi newsgroup,
is it possible to design some scrambling mechanism for Lattice SC FPGAs with some additional CPLD/FPGA ? Unfortunately there is no integrated circuit included yet to protect the bitstream.
Thank you for your opinions.
Rgds Andre
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