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system generator from Xilinx

Hello all, I just wanted to find out how good system generator software is? I can program in VHDL and would like to know if the SYS gen software would make life easier for me when it comes to designing DSP filters , FFTS or other DSP blocks. Does Xilinx provide IPs separately for the DSP blocks? If so then How different is it from using Xilinx IP in the design instead of sysgen blocks ? Any experience on system generator software would be helpful . Thanks, nbg

Reply to
nbg2006
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Since nobody wants to answer... I don't have any practical experience with sysgen, but here is what I know:

  1. It seems that Xilinx uses sysgen internally to develop their new cores. As a result some of the newer cores are not available through coregen, but only through sysgen or through a special request for a netlist. For example, take a look at their DUC core or at the Continuously Variable Fractional Rate Decimator described in the appnote XAPP936.

  1. Sysgen in concert with MATLAB Simulink seems to be a nice tool helping to visualize what happens with the signal. However I am not at all sure this tool won't be an annoying extra layer of complexity when designing low level interfaces between the modules.

  2. Sysgen + Simulink cost a lot of money.

/Mikhail

Reply to
MM

Well... that's not really true. Sure, there are certain pieces of DSP IP that are produced using System Generator, mostly as part of application notes / reference designs. But the majority of cores (i.e. generic, parameterizable, optimized, documented, extensively verified IP blocks) are delivered through coregen.

We aim to make IP available in the most convenient form possible. Obviously not everyone has or wants the System Generator tool, and therefore we continue to provide IP for users who have chosen a standard HDL design flow.

In any case, a block designed in Sysgen can be exported and incorporated into a larger design done in HDL, and a block design in HDL can similarly be incorporated into a Sysgen design.

Your other two points are valid though (hope I don't get into any trouble for saying that! :))

Cheers,

-Ben-

Reply to
Ben Jones

Thanks for talking to us Ben!

This is good to hear. Can I ask you then to move the DUC into coregen. It would be also very nice if one could choose complex input for the DDC and complex output for the DUC, as well as multichannel optimization.

Yes, but one needs to have Sysgen for that...

Thanks, /Mikhail

Reply to
MM

I wrote of my experience a while ago:

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I guess there's more blocks in there now, and the integration with AccellDSP might be of benefit, but we didn;t feel much benefit from it on the project we were doing.

Sysgen isn't *that* expensive if you are already Matlab/Simulink inclined.

--
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Reply to
Martin Thompson

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