Field-Programmable Gate Arrays

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suggest me the right fpga

hi everyone I am doing a fpga project for my engineering course completion. The project is to process an image caught b...
4 comments posted 19yrs
posted by shahmdk
4 comments posted 19yrs posted by shahmdk

Correction for hwicap_v1_00_a code

Not sure if anyone else will care to know about this, but I've found myself mentioning it to a few people, so I'll just...
2 comments posted 19yrs
posted by neil.steiner
2 comments posted 19yrs posted by neil.steiner

Final call for papers: Multi-conference

Submission deadline is: February 1st 2007 www.PromoteResearch.org The 2007 International Multi-Conference in Computer S...
0 comments posted 19yrs
posted by devipsr
0 comments posted 19yrs posted by devipsr

Altera EP2S60 rebooting itself

Hi. Sorry, I'm newbie here. What can cause such problem: after configuring device, it's working for about few seconds,...
2 comments posted 19yrs
posted by Dennis.Yurichev
2 comments posted 19yrs posted by Dennis.Yurichev

SPARC V7 CORE

Hi, Does anybody know if a SYNTHETISABLE Sparc V7 IP core is available ? I got the ERC32 free core which is useful for...
4 comments posted 19yrs
posted by nospam
4 comments posted 19yrs posted by nospam

NetBSD on Xilinx fpga (ported to ML403)

http://dspfpga.com/index.php?option=com_content&task=view&id=27&Itemid=9&lang=en Just thought it could be of interest to...
0 comments posted 19yrs
posted by pbdelete
0 comments posted 19yrs posted by pbdelete

Series DCM's and total Lock Time

Hi, I googled around a bit but could not find the answer. I am using Xilinx Spartan FPGA, with 2 DCM's in series to gen...
3 comments posted 19yrs
posted by moogyd
3 comments posted 19yrs posted by moogyd

Phasse Detector

Share please the circuit of the phase detector (I do not want to invent a bicycle). Any of the circuits laid out in an I...
13 comments posted 19yrs
posted by axalay
13 comments posted 19yrs posted by axalay

Im Hoping This Is What You Need

Hi, Are you tired and annoyed at low paying affiliate programs. Do you get paid $20 while the customer you referred mak...
0 comments posted 19yrs
posted by spread
0 comments posted 19yrs posted by spread

Timing Delay Definitions

The hyperlinks in Xilinx' Timing Analyzer do not go to valid web pages. I am using 8.2 with the latest SP. I've done a...
2 comments posted 19yrs
posted by mottoblatto
2 comments posted 19yrs posted by mottoblatto

"Gate" = ???

OK, I have been asked, many times, how an ASIC "gate" compares to a FPGA "gate." Now don't just groan, and hit ignore,...
5 comments posted 19yrs
posted by austin
5 comments posted 19yrs posted by austin

Beginner VHDL questions

Say in an if-statement I assign a value by: "temp
7 comments posted 19yrs
posted by jameswu
7 comments posted 19yrs posted by jameswu

ISE Simulator Error 222: SuSE 10.1 Linux

To fix the error you can also patch the xsim.h file under the Xilinx installation directory and use your brand new gcc 4...
2 comments posted 19yrs
posted by dibacco
2 comments posted 19yrs posted by dibacco