Field-Programmable Gate Arrays

Xilinx Ethernet MAC - working with DMA (EDK)

Hi all, I am having some difficulties working with the DMA of the ethernet mac. I've downloaded a ref. design of web-se...

0 comments posted 19yrs

posted by guybye

0 comments posted 19yrs posted by guybye

NGDBuild error

Hello I'm working on Xilinx virtex II Pro FPGA kit.I generated netlist for OR gate using JHDL, with a1 and a2 being inp...

1 comments posted 19yrs

posted by fyp.quadruples

1 comments posted 19yrs posted by fyp.quadruples

Disabling Interrupts/Context switching in Xilkernel

Hi, I looked through the Xilkernel documentation and Xilinx mentions a few times about enabling and disabling interrupt...

1 comments posted 19yrs

posted by RobotBuilder

1 comments posted 19yrs posted by RobotBuilder

Xilinx ML40x SRAM to/from Flash

Does any one have the VHDL code to transfer ZBT SRAM data to and from the Flash Memory? Seems like it should be a matte...

0 comments posted 19yrs

posted by bradsmallridge

0 comments posted 19yrs posted by bradsmallridge

regarding the usage of tri mode EMAC on virtex 4

Hi, I am trying to establish communication between PC and Virtex4 FX 12 mini module from www.memec.com.As I am new to t...

0 comments posted 19yrs

posted by bachimanchi

0 comments posted 19yrs posted by bachimanchi

Applications under MontaVista Linux on ML310

Greetings! I have a question regarding applications running on embedded Linux on an ML310. Getting things to work under...

0 comments posted 19yrs

posted by the.jd.in.space

0 comments posted 19yrs posted by the.jd.in.space

Setting VHDL standard in Xilinx ISE

Hi Does anyone here know, how to explicitly set which VHDL standard should be used by Xilinx ISE (actually, by XST I thi...

5 comments posted 19yrs

posted by wojtek.bocer

5 comments posted 19yrs posted by wojtek.bocer

Xilinx Platform Studio Evaluation Trial Expired (included in Spartan 3E Starter Kit)

Hello, I bought a Spartan 3E Starter kit which included a XPS 8.1 Evaluation Software. Now it has expired and I cannot...

6 comments posted 19yrs

posted by pbantunez

6 comments posted 19yrs posted by pbantunez

Digital AM/FM Receiver

Hi There! I am designing a digital AM/FM receiver in a Vertex-4 FPGA. I have designed the system blocks but have one qu...

4 comments posted 19yrs

posted by saurster

4 comments posted 19yrs posted by saurster

Question Regarding Look-Up Tables and Access Time/Levels of Logic

Is there a standard used for look-up table access time in terms of levels of logic? As an example, if I have a 2^8 x 8...

3 comments posted 19yrs

posted by aelbirt

3 comments posted 19yrs posted by aelbirt

FSL Questions

I have a custom IP module connected to an FSL. I connect the FSL_M_Data and FSL_M_Write to signals in my IP. The data b...

1 comments posted 19yrs

posted by mottoblatto

1 comments posted 19yrs posted by mottoblatto

Do you want to work in a highly complex FPGA/DSP product group?

Hi, My name is Sean Kawata and I am a Technical Recruiter for Volt Technical Resources. I have a prestigious client. I...

0 comments posted 19yrs

posted by skawata

0 comments posted 19yrs posted by skawata

Need advice to help improve timing on V4 FX

Hello, I can't meet the following constraint after playing around w/ some synthesis and implementation settings. Any sp...

7 comments posted 19yrs

posted by killerhertz

7 comments posted 19yrs posted by killerhertz

Read CLB information from NCD file

Dear all, Do you know how to read CLB information from NCD file to a readable text file ? I"m using Xilinx ISE8.1i to d...

4 comments posted 19yrs

posted by yuchiwai

4 comments posted 19yrs posted by yuchiwai

DCT/IDCT on FPGA

hi i am implementing DCT and IDCT on FPGA can any body give me some specific Block diagram you can send me the details o...

1 comments posted 19yrs

posted by prakash.akkasali

1 comments posted 19yrs posted by prakash.akkasali