Field-Programmable Gate Arrays

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DCT/IDCT on FPGA

hi i am implementing DCT and IDCT on FPGA can any body give me some specific Block diagram you can send me the details o...
1 comments posted 19yrs
posted by prakash.akkasali
1 comments posted 19yrs posted by prakash.akkasali

Virtex 4 SATA redux

I've read some of the heated discussions regarding Virtex 4 and SATA, but I'm still not sure what the answers are. My u...
2 comments posted 19yrs
posted by sam
2 comments posted 19yrs posted by sam

Radar pulse detection

Hi guys, I need your FPGA/DSP expertness in the following issue: I want to create a RADAR pulse detector (in FPGA) to w...
1 comments posted 19yrs
posted by me_2003
1 comments posted 19yrs posted by me_2003

ISE 9.1 sp1 and EDK 8.2 sp2

Hello, I have recently installed ISE9.1, since that moment I am no longer able to start EDK 8.2 . Has anybody had a simi...
2 comments posted 19yrs
posted by Karel.Deprez
2 comments posted 19yrs posted by Karel.Deprez

Interrupts and PPC/opb_intc

I have a hardware core that needs to be able to generate interrupts for all processors in the system (maximum of two PP...
4 comments posted 19yrs
posted by santner
4 comments posted 19yrs posted by santner

Floorplanning with Altera APEX20KE device

Hi, I'm trying to fix the location of some primitive cells (apex20ke_lcell) in a post-synthesis netlist for an Altera A...
0 comments posted 19yrs
posted by stefanti
0 comments posted 19yrs posted by stefanti

question abt DPRAM

Hi, I have an DPRAM which has writes taking place at a certain freq on port A (100 Mhz) & reads with a gated clock whic...
8 comments posted 19yrs
posted by bajajk
8 comments posted 19yrs posted by bajajk

ISE 9.1 Installation crash SuSE 10.2

Hello yesterday I ' ve tried to install ISE 9.1 on a openSuSE 10.2 system. Unfortunately the installation crashs after...
4 comments posted 19yrs
posted by gauckler
4 comments posted 19yrs posted by gauckler

Replacing/emulating an asynchronous FIFO

Hi, I am creating an FPGA (Spartan 3 XCS400) based replacement for one of our old board designs which uses IDT 7201 - h...
5 comments posted 19yrs
posted by darius
5 comments posted 19yrs posted by darius

Parallelism in HDL

Hi, I have one doubt : What is the need of parallelism/concurrency in the hardware description language ? I have seen s...
1 comments posted 19yrs
posted by sinu.nayak2001
1 comments posted 19yrs posted by sinu.nayak2001

EDK and multipleprocessors - Virtex2p

Has anyone successfully configured the two PowerPCs inside XUP2VP (virtex2Pro) using EDK?...as I know there are no feat...
0 comments posted 19yrs
posted by angeloaj
0 comments posted 19yrs posted by angeloaj

Altera ByteBlaster and SignalTap on Fedora Core

Is the Byte Blaster Cable and Signal Tap supported on Linux and more specifically on Fedora Core 5 or 6? All of my expe...
4 comments posted 19yrs
posted by schvantzkoph
4 comments posted 19yrs posted by schvantzkoph

Parameter File in Mixed Mode Designs

Hi newsgroup, I am trying to write a VHDL wrapper for a Verilog IP core which includes a "params.v" file: `define DDR2_...
0 comments posted 19yrs
posted by ALuPin
0 comments posted 19yrs posted by ALuPin