Digital AM/FM Receiver

Hi There! I am designing a digital AM/FM receiver in a Vertex-4 FPGA. I have designed the system blocks but have one question regarding digital filtering.

From a systemic point of view, we are using the DDC approach to

convert IF 45MHz down to baseband. After this we are using a 40MSPS A/ D to sample and output parallel 12-bit I, Q data to the FPGA. The FPGA front end has to have a LPF with a cut-off frequency of 5kHz. After the LPF, AM and FM need to be demodulated. I intend to do demodulation as follows FM -> (Q(n)I(n-1) - I(n)Q(n-1))/(I-Sq + Q-Sq) AM -> (I-Sq + Q-Sq) My question is: I need to do some decimation (to make my life easier when it comes to

5kHz LPF design)...what is the best way of doing this? I have read some material and it seems to point towards cascaded CIC filters. Please comment and also let me know if you notice any flaw in my design methodology. Moreover, due to my inexperience in this field, I wanted to know if decimation upstream would affect (adversely) my AM/ FM demodulation process.

cheers Morpheus

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morpheus skrev:

Hi Morpheus,

I designed a digital AM/FM receiver on a Virtex-2 FPGA a couple of years ago. Since I had a 210 Msps ADC (12 bits resolution) before the FPGA I did not do any DDC before the device. Instead I used a DDS internally and mixed the desired frequency down to baseband. For the decimation I used CIC filters in two stages and it worked good. I decimated the signal from ~200 MHz to about 128 kHz which was much more convenient for LP filtering. The CIC filters them selves has some LP properties too.

To extract the amplitude and phase from the I and Q I used a Cordic. Then it was quite easy to calculate the phase difference, and the amplitude is given.

Good luck!


Reply to
Johan Bernspang

If you are externally downconverting to baseband, there is no need to be sampling at 40 MS/sec, the DDC should have a low pass filter in it. If on the other-hand, all you have is a mixer, then the filtering makes sense. In that case, you probably want a CIC followed by one or more decimating FIR filters. In the receivers I've done, I sample the IF directly and do the downconversion in the FPGA rather than doing it outside. The CIC itself is a somewhat crude low pass filter (it has a sinx/x frequency characteristic) that makes it well suited for decimating, especially by large ratios.

The shortwave receiver shown on the home page of my website actually samples the RF directly and the FPGA (a Spartan2-100) does the tuning, down conversion and demodulation for AM and AM SSB. An FM demodulator can be added with little extra real-estate by using bit serial arithmetic. In that case, the RF is sampled at 40 MHz, and downconverted to complex base-band. The 40 MHz was dictated by the ADC's max sample rate. Considering the lack of an RF front end (the ADC input was connected to a long wire antenna through an antenna preamp) on this receiver it actually worked surprisingly well. I've done other designs that sample the RF or IF as high as 500MS/sec.

At a 5KHz cutoff, you are sampling at a very low (for FPGAs) rate, so the demodulation can be done bit serial. A CORDIC rotator is one way of deriving both AM and FM, as it produces amplitude and phase. Differencing the phase will get you the FM (you'll probably also want to put a DC blocker or add a frequency lock loop before the CORDIC to remove any residual carrier), and you may find you need an automatic gain control for the AM.

The decimation upstream is actually preferable since it lets you work at a lower sample rate, which in turn lightens the processing load.

Reply to
Ray Andraka

Hey Johan, I do get the architecture now. Most likely, I would follow the same technique as you did. I haven't used CORDIC before and even though I am reading up on it extensively, I was wondering if you could elaborate more (biased towards implementation). I do understand that I have to do this bit-serially and use the ARCTAN(x/y) function and subtract the current phase with the previous phase, to generate the FM signal. The AM can be generated though the Vector magnitude part of the CORDIC core. Any comments? Thanks MORPHEUS

Reply to

CORDIC doesn't have to be done bit-serially. That's just one method of implementing it. You can also do a parallel implementation, and in either case you can pipeline it or not. It has the typical tradeoffs of area and throughput.

Reply to
Eric Smith

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