I have a custom IP module connected to an FSL. I connect the FSL_M_Data and FSL_M_Write to signals in my IP. The data bus is ONLY
8 bits wide. I edited the populated mpd file to take out the slave FSL signals and bus refences (I don't need it in the custom IP), and I changed the bus width on the the data signal to 8 bits.I added an fsl xilinx core to the project and connected the M_Clk, S_Clk, RST, and Has_Data as appropriate. The S_Clk is connected to the OPB clock and the M_Clk is connected to the same clock that the custom logic is clocked with. The bus connections connect the custom IP as the master and the slave side is attached to the microblaze.
The custom IP asserts a signal when data is valid. That signal is connected to the M_Write signal. So when that is high, ONE BYTE of data is written on every clock. I am then using a little RS-232 terminal to experiment with reads. When I press the 'r' key, the code issues a 'mb_nbread' command and prints the byte out on the terminal.
The problem is that the bytes I read back are not what 'should' be written into the FSL FIFO. I am scoping (via ChipScope) the clocks, M_Write, and M_Data, and FSL_Has_Data. They all appear to be working right. I can hit 'r' as many times as there were bytes written and the FSL_Has_Data goes low as expected.
Like I said, the bytes back are incorrect. Once FSL_Has_Data goes low (after 'reading' all the bytes), I can repeatedly hit 'r' and the data returned is 'B8'. I am probably doing something wrong. Does anyone have any advice?
My concern is that the Import/Create wizard will not let me specify my specific setup. I have to hack it up to make the data width 8 bits. And I have to hack it up to take the slave link out of the custom IP.
Thanks!