Field-Programmable Gate Arrays

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ROC PORT

CAN ANY BODY EXPLAIN ROC PORT AND GIVE SOME INFORMATION ABOUT? HOW CAN WE ACTIVATE IT IN OUR VHDL CODE? THANK YOU
4 comments posted 19yrs
posted by saghaian
4 comments posted 19yrs posted by saghaian

MPD Files

Hello, I am trying to debug the sdram interface on a custom board I built. I need to look at some of the internal signa...
2 comments posted 19yrs
posted by hstello
2 comments posted 19yrs posted by hstello

low cost xilinx prom burner?

I need a production station that can (a) burn my xilinx xf08p serial prom and (b) xdownload some code to be burned to f...
7 comments posted 19yrs
posted by cepope
7 comments posted 19yrs posted by cepope

ACTEL ProAsic Plus

I have some very basic problems getting simple things to work on this platform. Is there a quirk of this product this i...
7 comments posted 19yrs
posted by charlesg77
7 comments posted 19yrs posted by charlesg77

Need help with VHDL simulation with SPW in Linux

Hi every one. I am newbie in FPGAs, although I can write VHDL. I already setup a copy of Cadence SPW 4.82 from my compa...
0 comments posted 19yrs
posted by dang_hut
0 comments posted 19yrs posted by dang_hut

System Requirement to run V4Lx200,v5lx330

Hi guys, Our comany trying to buy a new board with V4lx200 or v5lx330. >From the xilinx website it's recommended that 1...
0 comments posted 19yrs
posted by subin.82
0 comments posted 19yrs posted by subin.82

Testing FPGA

Hi guys, I am working in the FPGA's for the last one year. I never doubted the working of the FPGA, but now i want to k...
2 comments posted 19yrs
posted by subin.82
2 comments posted 19yrs posted by subin.82

best way to get 4xclk

Hi, What is the recommended way to get 4xClk from Clk? Xilinx recommends not to use cascaded DCMs for jitter & skew prob...
5 comments posted 19yrs
posted by krishna.janumanchi
5 comments posted 19yrs posted by krishna.janumanchi

need help on our thesis proposal in our school.

We are currently proposing to do a FPGA based fm receiver using VHDL. We are newbies in the VHDL programming and we are...
3 comments posted 19yrs
posted by rits11
3 comments posted 19yrs posted by rits11

Nexys from Digilent... aka, binge hacking

Recently I ordered a Nexys Spartan3-1000 / Cypress FX2 USB board from Digilent for work. It's been fun and I may well b...
3 comments posted 19yrs
posted by cs_posting
3 comments posted 19yrs posted by cs_posting

Xilinx ISE WebPack Simulation Problem

I am trying to perform a simple behavioral simulation of a baud rate clock generation module. The module is straightfor...
1 comments posted 19yrs
posted by scott.nortman
1 comments posted 19yrs posted by scott.nortman

LUT based virtex multiplier

Hi, I wonder if someone could suggest an efficient LUT based signed multiplication algorithm for Virtex FPGAs. I've imp...
2 comments posted 19yrs
posted by evilkidder
2 comments posted 19yrs posted by evilkidder

Where to start???

Hi, I'm very interested in starting to learn about fpgas. I tried finding if there was anything about it at local colle...
6 comments posted 19yrs
posted by bitsbytesandbugs
6 comments posted 19yrs posted by bitsbytesandbugs

Does Xilinx XST synthesize combinational divider?

I wrote a simple VHDL code using divide function. In Quartus II, it work fine. A LPM divider was synthesized. However,...
2 comments posted 19yrs
posted by junsong.liao
2 comments posted 19yrs posted by junsong.liao