Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Verilog: Simulating Transport Delays on Bidirectional Tristate Lines
When I started to write this, I wanted to ask how to model a bidirectional wire with transport delays but I've come up with a solution that works for my SDRAM sim so I'll post it here. I've done a...
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17 years ago
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Has anyone gotten the GSRD to run from Ace CF?
I can build other designs and have them work using the ACE CF, however the GSRD does not seem to kick off the software application. I'm very frustrated - is there an issue loading the external ddram...
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17 years ago
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Lattice / M-LVDS
Hi there, I've heard that some Lattice FPGAs support M-LVDS signalling. Did anyone has any experience with lattice M-LVDS? Are they true M-LVDS driver/receivers? What are the deviations from the...
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17 years ago
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ModelSim EDK Sim Problem
I am using the latest greatest Windows install of ModelSim SE. I have compiled all the ISE and EDK simulation libraries using the tools in command line mode. That is another story all together, but...
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17 years ago
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Do you like Virtex-5 ?
Do you like Virtex-5 ? Then please vote for it... The editors of Electronic Design News think Virtex-5 is an innovative product; they have nominated for their 17th Annual EDN Innovation Awards: the...
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17 years ago
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using shared vhdl code in customer ipif block
Hi, I have a small microblaze system with my own ipif peripheral. In this peripheral I want to use a vhdl block which is also used in another part of my project. Is this possible? Because when...
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17 years ago
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FFT IP ALTERA FORMAT
Hello, Do you know what is the format of the FFT IP 2.2.1 Altera Output ? It's not compliant with IEEE 754 floating point format I think that it have the exponent in 2's complement The mantissa in 2's...
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17 years ago
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EDK Simulation on NCSIM
Does anyone have a good recipe for simulating an EDK project in NC- Sim? I am looking at the NC Launch (GUI front end) revision and it is 05.40-s015. I am using EDK 8.2 with the latest service pack. I...
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17 years ago
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Can't be too thin or too rich or have too many ground pads
From anandtech's article () on the 80-core Intel Terascale chip: "The chip uses a LGA package like Intel's Core 2 and Pentium 4 processors, but features 1248 pins. Of the 1248 pins on the package, 343...
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17 years ago
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ML403 FPGA and CPLD
Hallo, I would connect virtex-4fx and cpld to test an i2c slave peripheral. Into virtex-4 I have programmed a small system with microblaze, opb_i2c, and some other peripherals. Into cpld I would...
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17 years ago
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Can't get the ACE to run software apps on the ML403
I've created a variant of the GSRD with a fairly large software application that runs great using the impact download and xmd debugger - However, I can't get the software application to run using the...
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17 years ago
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ppc405_1 and LED in EDK
Hey guys, I am using the XUP2VP Virtex2P board. and I couldnt be able to configure the second processor (ppc405_1) with LED using EDK. Does EDK support configuring ppc405_1?.. Angelo
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17 years ago
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Spartan 3 Output Driver Issue
Hello All, I have been having some trouble with a custom designed FPGA board based on the Xilinx Spartan 3 (XC3S400-FT256). I am hoping that someone here might be able to shed some light on the...
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17 years ago
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Xilinx Platform Studio adding Xilinx coreGen IP
Hi, I have an XPS project which allows me to fill BRAM (port A) with data over Ethernet. I then have some custom hardware written in VHDL in the pcores folder and listed in the project repository...
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17 years ago
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MGT free design papers.
Guys, I saw this from Steve Weir on SI-LIST and thought of you all! With special St. Valentine's love, Syms. xx (See! I _said_ a switcher works just fine!)
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17 years ago
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