Field-Programmable Gate Arrays

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Has anyone gotten the GSRD to run from Ace CF?

I can build other designs and have them work using the ACE CF, however the GSRD does not seem to kick off the software...
0 comments posted 19yrs
posted by davehays
0 comments posted 19yrs posted by davehays

Lattice / M-LVDS

Hi there, I've heard that some Lattice FPGAs support M-LVDS signalling. Did anyone has any experience with lattice M-LV...
1 comments posted 19yrs
posted by metinnn
1 comments posted 19yrs posted by metinnn

ModelSim EDK Sim Problem

I am using the latest greatest Windows install of ModelSim SE. I have compiled all the ISE and EDK simulation libraries...
1 comments posted 19yrs
posted by mottoblatto
1 comments posted 19yrs posted by mottoblatto

Do you like Virtex-5 ?

Do you like Virtex-5 ? Then please vote for it... The editors of Electronic Design News think Virtex-5 is an innovative...
30 comments posted 19yrs
posted by peter
30 comments posted 19yrs posted by peter

using shared vhdl code in customer ipif block

Hi, I have a small microblaze system with my own ipif peripheral. In this peripheral I want to use a vhdl block which i...
1 comments posted 19yrs
posted by someone
1 comments posted 19yrs posted by someone

FFT IP ALTERA FORMAT

Hello, Do you know what is the format of the FFT IP 2.2.1 Altera Output ? It's not compliant with IEEE 754 floating poi...
0 comments posted 19yrs
posted by patrick.melet
0 comments posted 19yrs posted by patrick.melet

EDK Simulation on NCSIM

Does anyone have a good recipe for simulating an EDK project in NC- Sim? I am looking at the NC Launch (GUI front end)...
1 comments posted 19yrs
posted by mottoblatto
1 comments posted 19yrs posted by mottoblatto

ML403 FPGA and CPLD

Hallo, I would connect virtex-4fx and cpld to test an i2c slave peripheral. Into virtex-4 I have programmed a small sys...
0 comments posted 19yrs
posted by mmm
0 comments posted 19yrs posted by mmm

ppc405_1 and LED in EDK

Hey guys, I am using the XUP2VP Virtex2P board. and I couldnt be able to configure the second processor (ppc405_1) with...
0 comments posted 19yrs
posted by angeloaj
0 comments posted 19yrs posted by angeloaj

Spartan 3 Output Driver Issue

Hello All, I have been having some trouble with a custom designed FPGA board based on the Xilinx Spartan 3 (XC3S400-FT2...
5 comments posted 19yrs
posted by bengineerd
5 comments posted 19yrs posted by bengineerd

Xilinx Platform Studio adding Xilinx coreGen IP

Hi, I have an XPS project which allows me to fill BRAM (port A) with data over Ethernet. I then have some custom hardwa...
3 comments posted 19yrs
posted by stephenmck
3 comments posted 19yrs posted by stephenmck

MGT free design papers.

Guys, I saw this from Steve Weir on SI-LIST and thought of you all! With special St. Valentine's love, Syms. xx http://w...
0 comments posted 19yrs
posted by symon_brewer
0 comments posted 19yrs posted by symon_brewer