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Xilinx Platform Studio adding Xilinx coreGen IP

Hi, I have an XPS project which allows me to fill BRAM (port A) with data over Ethernet. I then have some custom hardware written in VHDL in the pcores folder and listed in the project repository which uses the 2nd BRAM port (port B) to do some processing and write the output back to BRAM. This part of the project is working well. My problem is that I need to incorporate a Xilinx CoreGen IP core as a module in this custom hardware block and I cant figure out how to do this. I tried adding the .xmp file as an embedded sub-module to an ISE project but the 'Instantiation Template' that was produced didn't contain the output ports of the custom block that weren't connected to a bus. Similarly when I tried creating a peripheral (in XPS) the wizard would only let me connect to a bus and not directly to the 2nd unused port of the BRAM. I hope my explanation is clear. Any help on this would be great.

Thanks, S.

Reply to
stephenmck
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Instead of using the import wizard, I suggest that you read the "Platform Specification Format Manual" also known as UG131 located in the $EDK\doc directory. I used the import wizard for the first sample pcore that I created, but now I prefer to create all the EDK data files myself because I find it is more flexible.

There are some examples of how to use CoreGen from EDK in the Xilinx ChipScope cores in EDK. They use TCL files to create files for CoreGen and then call Coregen to create the core. Look in $EDK\hw \XilinxProcessorIPLib\pcores\chipscope_*\data for the TCl files to use as examples.

Regards,

John McCaskill

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Reply to
John McCaskill

If you just want to include a netlist generated by CoreGen in your XPS project, you will need to create a BBD (black box definition?) file in the data/ directory of the pcore you want to use the core in. You will also need to create a netlist/ directory to put your EDNs and NGCs in.

Matt

Reply to
Matt B

thanks for your help I've got it sorted now

Reply to
stephenmck

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