Field-Programmable Gate Arrays

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help read a pixel for picture

hi every body , my problem is how to read a pixel for a picture (a pixel is composed by three component Red, Green and...
2 comments posted 19yrs
posted by abaidik
2 comments posted 19yrs posted by abaidik

Instance Name Being Removed?

Hello, I'm having an instance being optimized away, although I'd like to keep the instance name hierarchy. I have "keep...
5 comments posted 19yrs
posted by killerhertz
5 comments posted 19yrs posted by killerhertz

XST ucf timespec

Hello! So the only ucf timing-related constraint I've ever really had cause to use is the PERIOD constraint, such as: N...
1 comments posted 19yrs
posted by jonas
1 comments posted 19yrs posted by jonas

OPB-to-PLB bridge

Hi, I need to access a PLB slave from the Microblaze CPU via the OPB-to- PLB bus. The PLB slave requires a cache line w...
1 comments posted 19yrs
posted by eascheiber
1 comments posted 19yrs posted by eascheiber

How to connect an IP to OPB bus??

Hi, I am working with Virtex-4. I have generated a VHDL code and need it to communicate it with Power PC and some other...
2 comments posted 19yrs
posted by sandip.gaikwad
2 comments posted 19yrs posted by sandip.gaikwad

Virtex-5 are available from distribution

As I mentioned before, Virtex-5 devices are plentifully available at Xilinx, and now also from Avnet and NuHorizon. The...
0 comments posted 19yrs
posted by peter
0 comments posted 19yrs posted by peter

Help with Partial Reconfiguration on Spartan3

Dear all, I am trying to perform a module based partial reconfiguration on a Spartan3 XC3S400 (on a 3SxLC board by MEME...
1 comments posted 19yrs
posted by lucaroccasalva
1 comments posted 19yrs posted by lucaroccasalva

apologia

All, I had posted: "How else is one measured, except by their commitments? V5 has met all dates. In fact, has exceeded...
2 comments posted 19yrs
posted by austin
2 comments posted 19yrs posted by austin

xilinx block ram synthesis

Hi Since Version 7.x xilinx xst is able to infer block ram out of appropriate vhdl statements. Unfortunately it is not...
12 comments posted 19yrs
posted by st
12 comments posted 19yrs posted by st

looking for the source VHDL for Jpeg 2000

Hello, I am just looking for the Jpeg 2000 source in VHDL, can anyone help me? thanx many! fred
2 comments posted 19yrs
posted by gnituil
2 comments posted 19yrs posted by gnituil

Bypass caps, X2Y and 'puddles'.

Hey Guys, It's a been a while since we had a bypass capacitor religious war, so I thought I'd stir things up a bit! Ser...
11 comments posted 19yrs
posted by symon_brewer
11 comments posted 19yrs posted by symon_brewer