Xilinx ISE Webpack 9.1 RTL schematic viewer problem


I have a problem with the latest Xilinx ISE webpack software (9.1, service pack 2). Nice thing is that the design (24bit CORDIC rotator written in VHDL) seems to run faster (181MHz) compared to version 8.2 of ISE webpack (164MHz). Not so nice thing is that the RTL viewer seems to screw up (or sort in a

*very strange* way) the compiled design. In 8.2 everything looks quite nice (3 n-bit adders, three n-bit FFs per stage drawn vertically), the structure is clearly visible. Other in 9.1. RTL viewer sorts the parts (first all n-bit FFs, then all adders, all drawn in a vertical chain). This completely clutters up the generated schematic. Additionally some blocks are even drawn wrong.

Is this a known problem or does my VHDL code probably compile different in different versions?



dnn engineering Robert M. Ganter
Belchenring 63          Tel:    +41(0)61 301 9538
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