XST ucf timespec

Hello! So the only ucf timing-related constraint I've ever really had cause to use is the PERIOD constraint, such as:

NET "CLKIN" TNM_NET = "CLKIN"; TIMESPEC "TS_CLKIN" = PERIOD "CLKIN" 19.9 ns HIGH 50 %;

I remember reading somewhere on the xilinx supprt site that you should always give yourself several hundred ps of wiggle-room, but I also remember reading that the tools take into account process and temp variations and so I should never try and be over-agressive in my timing constraints.

Does anyone have any experience one way or the other that they can share? What is your constraint strategy? I notice that the synthesis of my designs tends to be pretty sensitive to the actual constraint value -- devices that that synth at 19.8 ns might not at 19.9, even though it is a "slower" design.

Thanks! ...Eric

The place and route process for a relatively unconstained design starts with a random seed and works from there. Any change in the design or constraints can re-shape the process in an unpredictable way - like chaos. If you're seeing a lot of sensitivity to a small change in constraints it is possible that a little floorplanning will help the placement process a lot. Also if you don't meet constraints when you loosen them, try starting with a different "cost table" number (defaults to 1) or use multipass place&route.

My experience with PERIOD constraints is that often loosening the constraint when possible can help to increase the final frequency of the routed design. This is especially true of multi-clock designs where the tools need to trade off one constraint against another. But even in single clock designs I've seen cases where my PERIOD constraint might be at 7.5 nS and when finished the routed design meets 7.1 nS. But if I tried to set the PERIOD to 7.1 nS the final result would not meet timing.

HTH, Gabor