ERROR:HDLParsers:409 .... at left hand side. Please help

You didn't provide line numbers with your listing but look at the third line closely and you will see what might be causing the problem.

Am Donnerstag, 19. November 2015 17:24:13 UTC+1 schrieb snipped-for-privacy@gmail.com:

You did not provide the relevant part of code. "column" and "row" are outputs and therefore signals, the errormessage indicates you use them in variable assignment (row := ABC) instead of signal assignments (row

Here is my code,here is no errors and warnings, but even no warnings and no errors (i think adv7125 problem) it doesnot work.I have old ML405 board an d it use ADV7125,and monitor is Acer AL1511 used 1024X768,I use LED out for checking whether is reset works or not, and also checked for CLK (LED VGA_R, VGA_G => VGA_G, VGA_B => VGA_B ); C2 : clock port map (clk100MHz,clk65MHz); LED

my UCF file,

NET "clk100MHz" LOC = "AB14"; --clock from ML405 clock generator NET "VGA_CLK" LOC = "AC7"; --clock to ADV7125 NET "reset_n" LOC = "d6"; NET "LED" LOC = "A10"; #NET "LED1" LOC = "B10"; #NET "LED2" LOC = "F13"; ####################### VGA ######################

NET "VGA_B" LOC = "f4" ; NET "VGA_B" LOC = "j4" ; NET "VGA_B" LOC = "g9" ; NET "VGA_B" LOC = "j5" ; #NET "VGA_B" LOC = "h3" ;

NET "VGA_G" LOC = "j3" ; NET "VGA_G" LOC = "k7" ; NET "VGA_G" LOC = "k3" ; NET "VGA_G" LOC = "g10" ; #NET "VGA_G" LOC = "k6" ;

NET "VGA_R" LOC = "f3" ; NET "VGA_R" LOC = "h7" ; NET "VGA_R" LOC = "e3" ; NET "VGA_R" LOC = "g5" ; #NET "VGA_R" LOC = "d3" ; ##################### SYNCs ######################## NET "HSYNC" LOC = "C3" ; NET "VSYNC" LOC = "D4" ;

I had a look at the datasheet at

Maybe you also need to drive the "blank" pin, or the "psave"....

It would pay to check the schematic...

Hello , thank you for your answer. I generate psave,nsync,nblank and 5 common signals and it starts to work normal, thank you everyone !!!