Fully preposterous gate arranger

Is there synthesis software out there that'll take Verilog or other HDL
and generate a netlist of 7400-series logic?
To carry things one step further, if you were seriously contemplating
such a thing, of course you'd want the software to understand that chips
and boards are of finite sizes, that propagation delays between chips and
boards exist, and that board-board connections have finite numbers of
pins.
So -- has it been done, perhaps by someone with way too much time on
their hands? How big is an ARM M1 core when it's implemented in discrete
logic chips that are currently available in the DigiKey catalog? And how
fast?
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Tim Wescott
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Interesting idea, but moving in the opposite direction of progress (grin). You could probably make a technology library for a standard synthesis package, but handling the multiple gates/package might be a problem.
It would probably be about the size of a PDP11-34 and run at 10MHz instead of 50MHz, but this is very much a WAG.
BobH
Reply to
BobH
Xilinx tools allow you to design at schematic level with 74xx type parts, and then compile to logic equations. So, what you want is the inverse of that process!
Jon
Reply to
Jon Elson
Well, that's the point! Next, I'll ask that it generates schematics using vacuum tube logic.
I think it'd be fun. A Cosmac 1802 equivalent might be easier, though.
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Tim Wescott 
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Tim Wescott
How about doing logic using neon bulbs? I've considered doing a hardwired sudoku solver using discrete logic with neons. The final stage would be the readout. lol I don't want my whole living room to become a lab though.
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Rick
Reply to
rickman
Have you seen the original gas emission counting tubes? They had this arrangement where you'd trigger a clock wire which would make the glow jump from position 0 to position 1, etc. You could sense which pin had the glow and use it for carry, etc.
Apparently there were commercially viable computers that used these things, and carried out addition by counting up the accumulator while counting the addend down to zero.
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Tim Wescott 
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Tim Wescott
The reverse also works, so you can look at the generated RTL after inputting VHDL or Verilog but its mapping to the gates in the target chip, not discrete TTL. It also produce an IBIS Netlist...
I suspect it may be possible to adapt one of the open source synthesis tools to generate TTL Netlists..
Dave
Reply to
David Wade
Could you share your experience with open-source synthesis tools? I would be glad to have an overview on what is available and how it performs in practice!
Pere
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o pere o
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Tim Wescott 
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Tim Wescott
I don't think it would be so bad. I assume that many standard cells would have multiple outputs (eg Q and /Q) so presumably you could write a description that a 7400 takes 8 input variables and outputs 4 output variables - that an output doesn't depend on all the inputs isn't exactly unusual. Who knows how well it would do placement based on that description, but that's usual tools voodoo.
My guess would be this would work better with a tool like Synopsys Design Compiler (intended for standard cell gates) rather than an FPGA tool (that thinks about LUTs), but use whatever you have really.
Presumably you could use an ASIC design flow with appropriate design rules (set your ASIC technology to match your PCB layer stackup, tell it the spacing rules of your PCB house) and get it to route the PCB for you? Output Gerber instead of GDS-II and send for fab?
Hmm, that could be a fun way of teaching how to use the tools...
Theo
Reply to
Theo Markettos
Harking back to speed point above, the Harwell Computer is incredably slow. An experienced Hand Calculator operator can work just as fast, at least for a short period of time...
Dave G4UGM
Reply to
David Wade
Back in the day when I was actually building computers out of such logic 10MHz was a significant challenge.
Just thinking about makes me cringe. When I finally created a 10Mps special purpose ISA it was a real achievement. Tim clearly you have far too much time on your hands just thinking about such stuff:) Other than ... "With miniaturization we put all this stuff in there in the last 40 years." Why?
w..
Reply to
Walter Banks
Why? Why build vacuum-tube electronics? Why build hot rods out of cars from the 1930s?
Why not?
(Note that _I_ do not wish to be the one doing this...)
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Reply to
Tim Wescott
I've actually thought about this as well. I also thought about how good it would be to also build core memory and therefore construct a full Iron Age computer.
I would do this to create a known device with no non-inspectable components, which here means "no backdoors". Then I would use it to compile more integrated systems culminating with a fast FPGA-based device and/or a known safe compiler lineage.
However, the project is not a priority. :)
Reply to
Aleksandar Kuktin
I suspect that even those "iron age" computers had back doors.
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Tim Wescott
Don't confuse synthesis with placement and routing.
Some board-level schematic capture systems (like Cadence Concept/Alegro DE) compile a schematic into a list of "sections" (logical subcomponents) and then "package" these subcomponents into devices (e.g. four 2-input NAND gat es into one 7400 device) for layout, which can then re-assign subcomponents to "swap gates" between packages during PWB layout. The "packager" underst ands constraints like common logical pins between multiple sections (like t he common clock and OE pins on a '374 octal register) so that two gates (re gisters in the case of a '374) can only be packaged into the same device if they share the same clock and OE signals.
With such a back-end packaging system, the synthesis tool would only need t o map to single gates/functions, which would probably give better results, and could be "packaged" by a conventional schematic capture & layout system .
Andy
Reply to
jonesandy
Only in the absence of significant delays due to board layout. If you wanted to push the clock frequency, and especially if you were going to run multiple boards, then arranging things for best propagation delay would get -- interesting.
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Reply to
Tim Wescott
In any event, parameter extraction for timing analysis would be a real trick! It should at least be possible on a PCB, wire wrap would probably just be a default guess.
BobH
Reply to
BobH
It's possible - tools like HyperLynx do it. For multiple boards you can throw in the R-L-C of the interconnect as additional passive components in the model. If you're really fussy, Ansys will give you 3D E-M simulation to extract them from your 3D geometry.
What this workflow isn't is closed loop. While you can construct a toolchain:
HDL -> synthesis -> technology mapping -> schematic -> board layout -> parameter extraction
the design is roughly waterfall except perhaps the board layout stage, which is informed by timing extraction. In other words there is no mechanism to make changes to the logic mapping based on timing of placement: in the PCB tool you can pin or package swap but that's about it.
FPGA tools are better at going back up and redoing the synthesis if the place and route doesn't meet timing. PCB tools generally don't.
Theo
Reply to
Theo Markettos
Well, that gives us some more guidance for making our FPGA fully preposterous! To be fully preposterous, a gate arranger must be moving the 7400-series parts around on multiple boards and taking backplane delays into account.
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Tim Wescott 
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Tim Wescott

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