Field-Programmable Gate Arrays

Watchdog Timers for FPGA Designs

A recent thread in comp.arch.embedded concerns using watchdog timers. I made the point that they are used with software...

6 comments posted 10yrs

posted by gnuarm

6 comments posted 10yrs posted by gnuarm

Matlab-to-Gates for Xilinx

Does Xilinx still make a Matlab (not Simulink) -to-gates tool? I don't thi nk so, but I was just wondering. Not that I'...

3 comments posted 10yrs

posted by kevin.neilson

3 comments posted 10yrs posted by kevin.neilson

Help finding Xilinx software for HW-130 programmer

I am searching for some Xilinx programmer software for the HW-130 unit from around 1996-2000. Looking the the DOS versi...

7 comments posted 10yrs

posted by TimRegeant

7 comments posted 10yrs posted by TimRegeant

Deep Embedded Processor Board

The thread on spinning a 386 in an FPGA made me think about the FPGA boards available. I know you can find boards that...

5 comments posted 10yrs

posted by gnuarm

5 comments posted 10yrs posted by gnuarm

Online Writing Jobs / Jobs For Writers

We are a company looking for qualified individuals to help out with writing tasks such as: - short stories - movie scri...

0 comments posted 10yrs

posted by writingjobs205

0 comments posted 10yrs posted by writingjobs205

Simplistic AXI4-Lite to IPbus bridge

Hi, I found it useful to be able to control my IPbus ( https://svnweb.cern.ch/trac/cactus ) connected logic from an AXI...

0 comments posted 10yrs

posted by wzab01

0 comments posted 10yrs posted by wzab01

Challenges in data science which can be solved with FPGAs

Hi Everyone, I want to know what are the challenges in data science and cloud computing which are being faced today and...

3 comments posted 10yrs

posted by prasadp4009

3 comments posted 10yrs posted by prasadp4009

Do you understand what's at stake?

Do you understand what's at stake? If you do not let Jesus Christ take away your sins, then you will have to pay for th...

28 comments posted 10yrs

posted by rick.c.hodgin

28 comments posted 10yrs posted by rick.c.hodgin

VHDL Obfuscators, the Good, the Bad, and the Ugly

I have been looking at the various options for VHDL obfuscators. I have tried all of the free programs that I could fin...

2 comments posted 10yrs

posted by email.crj

2 comments posted 10yrs posted by email.crj

Atmels product selector

I've tried to open the product search in the CPLD product category several times in the last few days. I wanted to know...

3 comments posted 10yrs

posted by klammerj

3 comments posted 10yrs posted by klammerj

Using an FPGA to drive the 80386 CPU on a real motherboard

I have a desire to create an 80386 CPU in FPGA form, one which will plug in to the 132-pin socket of existing 80386 mot...

125 comments posted 10yrs

posted by rick.c.hodgin

125 comments posted 10yrs posted by rick.c.hodgin

Altera HSMC connector

Hello all. I'm looking for some information about Altera's FPGA. I have this Cyclone V GX dev board:...

18 comments posted 10yrs

posted by rick.c.hodgin

18 comments posted 10yrs posted by rick.c.hodgin

FPGA Internal or external USB PHY/SIE ??

We need to interface 8 to 16 embedded USB 2.0 devices to an FPGA. We could just use external ULPI transceivers but am w...

21 comments posted 10yrs

posted by sja

21 comments posted 10yrs posted by sja

Vivado MIG says "Design entry" is VERILOG, how to change to VHDL?

With Vivado 2015.4, I'm trying to add DDR3 memory to a Microblaze design. I add the Memory Interface Generator to the b...

1 comments posted 10yrs

posted by spacewar

1 comments posted 10yrs posted by spacewar

Simplify handling of SW accessible registers in FPGA

Save lots of work - Auto-generate register related code and documentation, and - Keep SW, FPGA and Documentation synchr...

0 comments posted 10yrs

posted by espen.tallaksen

0 comments posted 10yrs posted by espen.tallaksen