Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

Freelance engineer in barcelona area

We are looking for a freelance engineer in barcelona area. Please contact to my e-Mail.
0 comments posted 10yrs
posted by jmib1961
0 comments posted 10yrs posted by jmib1961

Altera MAX10 image capture application

We are interested in finding someone to help develop an FPGA image capture application. We are using Altera's MAX10 FPG...
1 comments posted 10yrs
posted by wiildland
1 comments posted 10yrs posted by wiildland

Fully preposterous gate arranger

Is there synthesis software out there that'll take Verilog or other HDL and generate a netlist of 7400-series logic? To...
20 comments posted 10yrs
posted by tim
20 comments posted 10yrs posted by tim

Opinions, on this newfangled thing, please

I just ran across this: http://www.eetimes.com/author.asp?section_id=36&doc_id=1328618&_mc=sm_eet_editor_maxmaxfield&ho...
6 comments posted 10yrs
posted by seemywebsite
6 comments posted 10yrs posted by seemywebsite

hamsterworks + lauriVosandi + X = Error

Hello i am new in vhdl, but try it, I want to make pipe between OV7670 and monitor, best thing is to use code o f Hamst...
9 comments posted 10yrs
posted by abirov
9 comments posted 10yrs posted by abirov

FPGA for a beginner

I know this subject is very repetitive, but It's very confusing to me. I'm familiar to verilog coding and digital circu...
8 comments posted 10yrs
posted by hamidkavianathar
8 comments posted 10yrs posted by hamidkavianathar

modulo 2**32-1 arith

Hello. I need to add two unsigned numbers modulo 2**32-1. Now it's done in very inefficient way: at first clock cycle t...
46 comments posted 10yrs
posted by stebanoid
46 comments posted 10yrs posted by stebanoid

Error in converting code to VHDL

Hi, Can some one please help out.Thanks. I am trying to convert below code to VHDL using HDL Coder but getting error .P...
0 comments posted 10yrs
posted by engr.jamilhayder
0 comments posted 10yrs posted by engr.jamilhayder

Simulation vs Synthesis

So I have a partly-complete design for a 6502 CPU, it's simulating just fin e for the implemented opcodes, but when I r...
67 comments posted 10yrs
posted by google
67 comments posted 10yrs posted by google

problem with impact

Hello friends I have a fpga spartan-3 development board that only has a parallel port for JTAG. I used a parallel to us...
1 comments posted 10yrs
posted by s.mohsen.shahabi
1 comments posted 10yrs posted by s.mohsen.shahabi

Nandland Go Board - Your FPGA Playground

There's a new FPGA development board on Kickstarter. It's called the Nandl and Go Board, and it aims to be an inexpensi...
1 comments posted 10yrs
posted by russellmerrick
1 comments posted 10yrs posted by russellmerrick

ML405 Xilinx ISE 14.7

Dear all first of all want thanx to everyone who belong to this forum and give help to each other. I checked ML405's sc...
3 comments posted 10yrs
posted by abirov
3 comments posted 10yrs posted by abirov